TSPC603RVA8LC Atmel, TSPC603RVA8LC Datasheet
TSPC603RVA8LC
Specifications of TSPC603RVA8LC
Related parts for TSPC603RVA8LC
TSPC603RVA8LC Summary of contents
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Features • Superscalar (3 Instructions per Clock Peak) • Dual 16 KB Caches • Selectable Bus Clock • 32-bit Compatibility PowerPC Implementation • On-chip Debug Support • Nap, Doze and Sleep Power Saving Modes • Device Offered in Cerquad, CBGA ...
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... Screening/Quality/Packaging This product is manufactured in full compliance with: • HiTCE CBGA according to Atmel Standards • CI-CGA 255 and Cerquad: MIL-PRF-38535 class Q or according to Atmel standards • CBGA 255: Upscreenings based upon Atmel standards • CBGA, CI-CGA, HiTCE packages: – Full military temperature range (T – ...
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Block Diagram Figure 3-1. 4. Overview The 603R is a low-power implementation of the PowerPC microprocessor family of Reduced Instruction Set Computing (RISC) microprocessors. The 603R implements the 32-bit portion of the PowerPC architecture, which provides 32-bit effective addresses, ...
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Load/Store Unit (LSU) • a System Register Unit (SRU) The ability to execute five instructions in parallel and the use of simple instructions with rapid execution times yield high efficiency and throughput for 603R-based systems. Most integer instructions ...
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... POWER SUPPLY INDICATOR 6. Detailed Specifications This specification describes the specific requirements for the microprocessor TSPC603R, in compliance with MIL-STD-883 class B or Atmel standard screening. 7. Applicable Documents 1. MIL-STD-883: Test methods and procedures for electronics 2. MIL-PRF-38535: General specifications for microcircuits The microcircuits are in accordance with the applicable documents and as specified herein. ...
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Design and Construction 7.1.1 Terminal Connections Depending on the package, the terminal connections are as shown in Table 10-4 on page 49, Figure 15-4 on page 52 7.1.2 Lead Material and Finish Lead material and finish shall be as ...
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Thermal Characteristics 8.1 CBGA 255 and CI-CGA 255 Packages The data found in this section concerns 603R devices packaged in the 255-lead 21 mm multi-layer ceramic (MLC) and ceramic BGA package. Data is included for use with a Thermal- ...
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Figure 8-1. Rsa (°C/W) Assuming an air velocity of 1 m/sec, the associated overall thermal resistance and junction tem- perature, found in Table 8-1. Configuration With 2328B heat sink Vendors such as Aavid, Thermalloy wide range of thermal performance. 8.2 ...
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Thermal Management Example The junction temperature can be calculated from the junction to ambient thermal resistance, as follows: Junction temperature Where the power dissipated by the device Because ...
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Programmable Power Modes The 603R provides four programmable power states, full power, doze, nap and sleep. The soft- ware selects these modes by setting one (and only one) of the three power saving mode bits. The hardware can enable ...
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Functional units are clocked only when needed • No software or hardware intervention required after mode is set • Software/hardware and performance are transparent Doze Mode The doze mode disables most functional units but maintains cache coherency by enabling ...
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Sleep Mode Sleep mode consumes the least amount of power of the four modes since all functional units are disabled. To conserve the maximum amount of power, the PLL may be disabled and the SYSCLK may be removed. Due to ...
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... To calculate the power consumption at low temperature (-55°C), use a factor of 1.25. 9.6 Marking Each microcircuit is legible and permanently marked with at least the following information: • Atmel logo • Manufacturer’s part number • Class B identification if applicable • Date code of inspection lot • ...
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Figure 10-1. CBGA 255, HiTCE CBGA 255 and CI–CGA 255 Top View Substrate Assembly TSPC603R 14 Pin matrix top view ...
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Pinout Listing Table 10-1. Power and Ground Pins V DD PLL (AV ) A10 DD F06, F08, F09, F11, G07, G10, H06, H08, H09, H11, (1) Internal Logic ( J06, J08, J09, J11, K07, K10, L06, L08, ...
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Table 10-2. Signal Pinout Listing (Continued) Signal Name CBGA, HiTCE CBGA and CI-CGA Pin Number GBL F01 HRESET A07 INT B15 (1) L1_TSTCLK D11 (1) L2_TSTCLK D12 (1) LSSD_MODE B10 MCP C13 PLL_CFG[0-3] A08, B09, A09, D09 QACK D03 QREQ ...
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CERQUAD 240 Package Figure 10-2. CERQUAD 240: Top View GBL VDD OGND 8 GND 9 OVDD 10 A11 11 A13 12 A15 13 VDD 14 A17 ...
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Pinout Listing Table 10-3. Power and Ground Pins VCC PLL (AV ) 209 DD 4, 14, 24, 34, 44, 59, 122, 137, 147, 157, 167, 177, Internal Logic 207 10, 20, 35, 45, 54, 61, 70, 79, 88, 96, ...
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Table 10-4. Signal Pinout Listing (Continued) Signal Name CERQUAD Pin Number INT 188 (1) L1_TSTCLK 204 (1) L2_TSTCLK 203 (1) LSSD_MODE 205 MCP 186 PLL_CFG[0-3] 213, 211, 210, 208 QACK 235 QREQ 31 RSRV 232 SMI 187 SRESET 189 SYSCLK ...
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Table 10-5. Address and Data Bus Signal Index for Cerquad, CBGA 255 and CI-CGA 255 Packages Signal Name Abbreviation Address Bus A[0-31] Data Bus DH[0-31] Data Bus DL[0-31] Table 10-6. Signal Index for Cerquad, CBGA 255, HiTCE CBGA 255 and ...
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Table 10-6. Signal Index for Cerquad, CBGA 255, HiTCE CBGA 255 and CI-CGA 255 Packages (Continued) Signal Name Abbreviation Global GBL Hard Reset HRESET Interrupt INT LSSD_MODE Factory Test L1_TSTCLK L2_TSTCLK Machine Check MCP Interrupt PLL Configuration PLL_CFG[0-3] Power supply ...
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Table 10-6. Signal Index for Cerquad, CBGA 255, HiTCE CBGA 255 and CI-CGA 255 Packages (Continued) Signal Name Abbreviation Transfer Start TS Transfer Type TT[0-4] Write-through WT 11. Electrical Characteristics 11.1 General Requirements All static and dynamic electrical characteristics specified ...
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Leakage currents are measured for nominal OV and OV vary by either +5% or -5%) DD 11.3 Dynamic Characteristics 11.3.1 Clock AC Specifications Table 11-2 Table 11-2. Clock AC Timing Specifications -55°C ≤ T ≤ 125°C C Figure Number ...
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Input AC Specifications Table 11-3 and Figure Table 11-3. Input AC Timing Specifications -55°C ≤ T ≤ 125°C C Figure Number Characteristics Address/data/transfer attribute inputs valid to 10a SYSCLK (input setup) 10b All other inputs valid to SYSCLK (input ...
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Figure 11-3. Mode Select Input Timing Diagram 11.3.3 Output AC Specifications Table 11-4 Table 11-4. Output AC Timing Specifications 55°C ≤ T ≤ 125°C C Number Characteristics SYSCLK to output driven (output 12 enable time) SYSCLK to output valid (5.5V ...
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Notes: 1. All output specifications are measured from the 1.4V of the rising edge of SYSCLK to the TTL level (0.8V or 2V) of the signal in question. Both input and output timings are measured at the pin. See 2. ...
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JTAG AC Timing Specifications Table 11-5. JTAG AC Timing Specifications (independent of SYSCLK pF, -55°C ≤ T GND = 0V Number Characteristics TCK frequency of operation 1 TCK cycle time 2 TCK clock pulse width ...
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Figure 11-7. Boundary-scan Timing Diagram Data Outputs Data Outputs Data Outputs Figure 11-8. Test Access Port Timing Diagram 12. Functional Description 12.1 PowerPC Registers and Programming Model The PowerPC architecture defines register-to-register operations for most computational instruc- tions. Source operands ...
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Having access to privilege instructions, registers, and other resources allows the operating sys- tem to control the application environment (providing virtual memory and protecting operating system and critical machine resources). Instructions that control the state of the processor, the address ...
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Special-purpose Registers (SPRs) The powerPC operating environment architecture defines numerous special-purpose registers that serve a variety of functions, such as providing controls, indicating status, configuring the processor, and performing special operations. During normal execution, a program can access the ...
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The Time Base register (TB 64-bit register that maintains the time of day and – The Processor Version Register (PVR 32-bit, read-only register that identifies – Block Address Translation (BAT) arrays - The PowerPC architecture ...
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Figure 12-1. PowerPC Microprocessor Programming Model – Register USER MODEL General-purpose Registers GPR0 GPR1 GPR31 Floating-point Registers FPR0 FPR1 GPR31 Condition Register CR Floating-point Status and Control Register FPSCR XER XER SPR1 Link Register LR SPR8 Count Register CTR SPR9 ...
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Instruction Set and Addressing Modes The following subsections describe the PowerPC instruction set and addressing modes in general. 12.2.1 PowerPC Instruction Set and Addressing Modes All PowerPC instructions are encoded as single-word (32-bit) opcodes. Instruction formats are consistent among ...
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Memory Control Instructions segment registers – Supervisor-level cache management instructions – User-level cache instructions – Segment register manipulation instructions – Translation lookaside buffer management instructions Note that this grouping of the instructions does not indicate which execution unit executes ...
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PowerPC 603R Microprocessor Instruction Set The 603R instruction set is defined as follows: • The 603R provides hardware support for all 32-bit PowerPC instructions. • The 603R provides two implementation-specific instructions used for software table search operations following TLB ...
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The instruction cache also consists of 128 sets of 4 lines, and each line consists of 32 bytes, an address tag, and a valid bit. The instruction cache may not be written to except through a line fill operation. The ...
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Exception Model The following subsections describe the PowerPC exception model and the 603R implementation. 12.3.4 PowerPC Exception Model The PowerPC exception mechanism allows the processor to change to supervisor state as a result of external singles, errors, or unusual ...
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Synchronous, Imprecise – the PowerPC architecture defines two imprecise floating-point exception modes, recoverable and nonrecoverable. Even though the 603R provides a means to enable the imprecise modes, it implements these modes identically to the precise mode (That is, all ...
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Table 12-2. Exceptions and Conditions (Continued) Vector Offset Exception Type (hex) DSI 00300 ISI 00400 External interrupt 00500 Alignment 00600 5410B–HIREL–09/05 Causing Conditions The cause of a DSI exception can be determined by the bit settings in the DSISR, listed ...
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Table 12-2. Exceptions and Conditions (Continued) Vector Offset Exception Type (hex) Program 00700 Floating-point 00800 unavailable Decrementer 00900 Reserved 00A00–00BFF System call 00C00 Trace 00D00 Reserved 00E00 Reserved 00E10–00FFF Instruction 01000 translation miss Data load 01100 translation miss Data store ...
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Table 12-2. Exceptions and Conditions (Continued) Vector Offset Exception Type (hex) Instruction address 01300 breakpoint System management 01400 interrupt Reserved 01500–02FFF 12.4 Memory Management The following subsections describe the memory management features of the PowerPC architec- ture, and the 603R ...
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The 603R’s TLBs are 64-entry, 2-way set-associative caches that contain instruction and data address translations. The 603R provides hardware assistance for software table search opera- tions through the ashed page table on the TLB misses. The supervisor software can invalidate ...
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... Microcircuits are prepared for delivery in accordance with MIL-PRF-38535. 13.2 Certificate of Compliance Atmel offers a certificate of compliance with each shipment of parts, affirming the products are in compliance with the MIL-STD-883 standard and guaranteeing the parameters that are not tested at temperature extremes for the entire temperature range. ...
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In Table scale represents the PLL-CFG[0-3] signals. For a given SYSCLK (bus) frequency, the PLL configuration signals set the internal CPU and VCO frequency of operation. Table 13-1. CPU Frequencies for Common Bus Frequencies and Multipliers CPU Frequency in MHZ ...
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Bus-to-Core PLL_CFG[0-3] Multiplier 1010 4x 0111 4.5x 1011 5x 1001 5.5x 1101 6x 0011 1111 Notes: 1. Some PLL configurations may select bus, CPU or VCO frequencies which are not supported PLL-bypass mode, the SYSCLK input signal clocks ...
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Decoupling Recommendations Due to the 603e’s dynamic power management feature, large address and data buses, and high operating frequencies, the 603e can generate transient power surges and high frequency noise in its power supply, especially while driving large capacitive ...
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Package Mechanical Data The following sections provide the package parameters and mechanical dimensions for the CBGA, HiTCE CBGA and the Cerquad packages. 15.1 HiTCE CBGA Package Parameters The package parameters are as provided in the following list. The package ...
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Mechanical Dimensions of the HiTCE CBGA Package Figure 15-1 HiTCE CBGA package. Figure 15-1. Mechanical Dimensions of the HiTCE CBGA Package Ball A1 Index 0 ...
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CBGA Package Parameters The package parameters are as provided in the following list. The package type is 21 mm, 255-lead Ceramic Ball Grid Array (CBGA). Package outline Interconnects Pitch Maximum module height 15.2.1 Mechanical Dimensions of the CBGA Package ...
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CI-CGA Package Parameters The package parameters are as provided in the following list. The package type is 21 mm, 255-lead ceramic ball grid array (CI-CGA). Package outline Interconnects Pitch Typical module height 15.3.1 Mechanical Dimensions of the CI-CGA Package ...
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Figure 15-3. Mechanical Dimensions and Bottom Surface Nomenclature of the CI-CGA Package A1 CORNER B 2X 0.200 - 255X D 0.300 S ...
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CERQUAD 240 Package Figure 15-4. Mechanical Dimensions of the Wire-bond CERQUAD Package Die TOP U 180 181 240 tips 0. TSPC603R 52 Wire Bonds Ceramic ...
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... Ordering Information of the CERQUAD 240 Package TS (X) Prefix Prototype Type Temperature range -55, +125˚C V: -40, +110˚ +70˚C Package CERQUAD Note: For availability of the different versions, contact your Atmel sales office. 5410B–HIREL–09/05 (X) PC603R Screening level Standard B/Q: MIL-PRF-38535, class Q U: Upscreening PC603R ...
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... Atmel customers using or selling these products for use in such applications their own risk and agree to fully indemnify Atmel for any damages resulting from such improper use or sale. 18. Document Revision History Table 18-1 Table 18-1 ...
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Table of Contents Features .................................................................................................... 1 Features Specific to CBGA 255, CBGA HiTCE 255 and CI-CGA 255 ... 1 Features Specific to Cerquad ................................................................. 1 1 Description ............................................................................................... 1 2 Screening/Quality/Packaging ................................................................. 2 3 Block Diagram .......................................................................................... 3 4 Overview ...
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Functional Description .......................................................................... 28 13 Preparation for Delivery ........................................................................ 43 14 System Design Information .................................................................. 45 15 Package Mechanical Data ..................................................................... 47 16 Ordering Information ............................................................................. 53 17 Definitions .............................................................................................. 54 18 Document Revision History .................................................................. 54 TSPC603R ii ...
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... Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI- TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT ...
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TSPC603R iv 5410B–HIREL–09/05 ...