TSPC603RVA8LC Atmel, TSPC603RVA8LC Datasheet - Page 12

• Manufacturer Part Number: TSPC603RVA8LC
• Description: IC MPU 32BIT 8MHZ 240CERQUAD
• Manufacturer: Atmel

Specifications of TSPC603RVA8LC

• Processor Type: PowerPC 603e 32-Bit RISC
• Speed: 200MHz
• Voltage: 2.5V
• Mounting Type: Surface Mount
• Package / Case: 240-Cerquad
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

9.4
12
Power Management Software Considerations
TSPC603R
Sleep Mode
Sleep mode consumes the least amount of power of the four modes since all functional units are
disabled. To conserve the maximum amount of power, the PLL may be disabled and the
SYSCLK may be removed. Due to the fully static design of the 603R, the internal processor
state is preserved when no internal clock is present. Because the time base and decrementer
are disabled while the 603R is in sleep mode, the 603R’s time base contents will have to be
updated from an external time base following sleep mode if accurate time-of-day maintenance is
required. Before the 603R enters the sleep mode, the 603R will assert the QREQ signal to indi-
cate that it is ready to disable bus snooping. When the system has ensured that snooping is no
longer necessary, it will assert QACK and the 603R will enter the sleep mode.
In this mode:
Since the 603R is a dual issue processor with out-of-order execution capabilities, care must be
taken with the way the power management mode is entered. Furthermore, nap and sleep modes
require all outstanding bus operations to be completed before the power management mode is
entered. Normally, during the system configuration time, one of the power management modes
would be selected by setting the appropriate HID0 mode bit. Later on, the power management
mode is invoked by setting the MSR[POW] bit. To provide a clean transition into and out of the
power management mode, the stmsr[POW] should be preceded by a sync instruction and fol-
lowed by an isync instruction.
• All functional units are disabled (including bus snooping and time base)
• All non-essential input receivers are disabled
• Sleep mode sequence
• There are several methods for returning to full-power mode
• The PLL may be disabled and SYSCLK may be removed while in sleep mode
• Return to full-power mode after PLL and SYSCLK disabled in sleep mode
– Internal clock regenerators are disabled
– The PLL is still running (see below)
– Set sleep bit (HID0[10] = 1)
– 603R asserts quiesce request (QREQ)
– System asserts quiesce acknowledge (QACK)
– 603R enters sleep mode after several processor clocks
– Assert INT, SMI, or MCP interrupts
– Assert hard reset or soft reset
– Enable SYSCLK
– Reconfigure PLL into the desired processor clock mode
– System logic waits for PLL startup and relock time (100 µs)
– System logic asserts one of the sleep recovery signals (for example, INT or SMI)
5410B–HIREL–09/05