TSPC603RVGH8LC Atmel, TSPC603RVGH8LC Datasheet - Page 21

• Manufacturer Part Number: TSPC603RVGH8LC
• Description: IC MPU 32BIT 8MHZ 255CBGA
• Manufacturer: Atmel

Specifications of TSPC603RVGH8LC

• Processor Type: PowerPC 603e 32-Bit RISC
• Speed: 200MHz
• Voltage: 2.5V
• Mounting Type: Surface Mount
• Package / Case: 255-CBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

Table 10-6.
5410B–HIREL–09/05
Signal Name
Global
Hard Reset
Interrupt
Factory Test
Machine Check
Interrupt
PLL Configuration
Power supply indicator
Quiescent
Acknowledge
Quiescent Request
Reservation
System Management
Interrupt
Soft Reset
System Clock
Test Clock
Transfer Acknowledge
Timebase Enable
Transfer Burst
Transfer Code
Test Clock
Test Data Input
Test Data Output
Transfer Error
Acknowledge
TLBI Sync
Test Mode Select
Test Reset
Transfer Size
Signal Index for Cerquad, CBGA 255, HiTCE CBGA 255 and CI-CGA 255 Packages (Continued)
Abbreviation
GBL
HRESET
INT
LSSD_MODE
L1_TSTCLK
L2_TSTCLK
MCP
PLL_CFG[0-3]
VOLTDETGND
QACK
QREQ
RSRV
SMI
SRESET
SYSCLK
CLK_OUT
TA
TBEN
TBST
TC[0-1]
TCK
TDI
TDO
TEA
TLBISYNC
TMS
TRST
TSIZ[0-2]
Signal Function
If output, a transaction is global
If input, a transaction must be snooped by the 603R
Initiates a complete hard reset operation
Initiates an interrupt if bit EE of MSR register is set
LSSD test control signal for factory use only
LSSD test control signal for factory use only
LSSD test control signal for factory use only
Initiates a machine check interrupt operation if the bit ME of MSR register and
bit EMCP of HID0 register are set
Configures the operation of the PLL and the internal processor clock frequency
Available only on BGA package
Indicates to the power supply that a low-voltage processor is present.
All bus activity has terminated and the 603R may enter a quiescent (or low
power) state
Is requesting all bus activity normally to enter a quiescent (low power) state
Represents the state of the reservation coherency bit in the reservation
address register
Initiates a system management interrupt operation if the bit EE of MSR register
is set
Initiates processing for a reset exception
Represents the primary clock input for the 603R, and the bus clock frequency
for 603R bus operation
Provides PLL clock output for PLL testing and monitoring
A single-beat data transfer completed successfully or a data beat in a burst
transfer completed successfully
The timebase should continue clocking
If output, a burst transfer is in progress
If input, when snooping for single-beat reads
Special encoding for the transfer in progress
Clock signal for the IEEE P1149.1 test access port (TAP)
Serial data input for the TAP
Serial data output for the TAP
A bus error occurred
Instruction execution should stop after execution of a tlbsync instruction
Selects the principal operations of the test-support circuitry
Provides an asynchronous reset of the TAP controller
For memory accesses, these signals along with TBST indicate the data
transfer size for the current bus operation
TSPC603R
Signal
Type
I/O
Input
Input
Input
Input
Input
Input
Input
Output
Input
Output
Output
Input
Input
Input
Output
Input
Input
I/O
Output
Input
Input
Output
Input
Input
Input
Input
I/O
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