TSPC603RVGH8LC Atmel, TSPC603RVGH8LC Datasheet - Page 4

• Manufacturer Part Number: TSPC603RVGH8LC
• Description: IC MPU 32BIT 8MHZ 255CBGA
• Manufacturer: Atmel

Specifications of TSPC603RVGH8LC

• Processor Type: PowerPC 603e 32-Bit RISC
• Speed: 200MHz
• Voltage: 2.5V
• Mounting Type: Surface Mount
• Package / Case: 255-CBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

5. Signal Description
4
TSPC603R
The ability to execute five instructions in parallel and the use of simple instructions with rapid
execution times yield high efficiency and throughput for 603R-based systems. Most integer
instructions execute in one clock cycle. The FPU is pipelined so a single-precision multiply-add
instruction can be issued every clock cycle.
The 603R provides independent on-chip, 16 Kbyte, four-way set-associative, physically
addressed caches for instructions and data, as well as on-chip instruction and data Memory
Management Units (MMUs). The MMUs contain 64-entry, two-way set-associative, Data and
Instruction Translation Lookaside Buffers (DTLB and ITLB) that provide support for
demand-paged virtual memory address translation and variable-sized block translation. The
TLBs and caches use a Least Recently Used (LRU) replacement algorithm. The 603R also sup-
ports block address translation through the use of two independent Instruction and Data Block
Address Translation (IBAT and DBAT) arrays of four entries each. Effective addresses are com-
pared simultaneously with all four entries in the BAT array during block translation. In
accordance with the PowerPC architecture, if an effective address hits in both the TLB and BAT
array, the BAT translation has priority.
The 603R has a selectable 32- or 64-bit data bus and a 32-bit address bus. The 603R interface
protocol allows multiple masters to compete for system resources through a central external
arbiter. The 603R provides a three-state coherency protocol that supports the exclusive, modi-
fied, and invalid cache states. This protocol is a compatible subset of the MESI
(Modified/Exclusive/Shared/Invalid) four-state protocol and operates coherently in systems that
contain four-state caches. The 603R supports single-beat and burst data transfers for memory
accesses, and supports memory-mapped I/Os.
The 603R uses an advanced, 0.29 µm 5-metal-layer CMOS process technology and maintains
full interface compatibility with TTL devices.
Figure 5-1 on page
TSPC603R and indicate signal functions. The test signals, TRST, TMS, TCK, TDI and TDO,
comply with the subset P-1149.1 of the IEEE testability bus standard.
The three signals LSSD_MODE, LI_TSTCLK and L2_TSTCLK are test signals for factory use
only and must be pulled up to V
• a Load/Store Unit (LSU)
• a System Register Unit (SRU)
5,
Table 10-5
DD
for normal machine operations.
and
Table 10-6 on page 20
describe the signals on the
5410B–HIREL–09/05