Z8018110FEC Zilog, Z8018110FEC Datasheet
Z8018110FEC
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Z8018110FEC Summary of contents
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... Controller (SCC), a Z80 CTC, two 8-bit general-pur- pose parallel ports, and two chip select signals, into a single 100-pin Quad Flat Pack (QFP) package (Figures 1 and 2). Created using Zilog's patented Superintegration methodology of combining proprietary IC cores and cells, this high-end intelligent peripheral controller is well-suited ...
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... Zilog GENERAL DESCRIPTION (Continued) D7-D0 Z80180 Compatible Control Core A19-A0 Glue Logic A19-A12 Address Decode /ROMCS Logic /RAMCS Z80181 = Z180 + SCC/2 + CTC + PIA 2-2 (1 Channel) Figure 1. Z80181 Functional Block Diagram PS009701-0301 MART CCESS ONTROLLER Tx Data SCC Rx Data Modem/Control 8 Signals CTC PIA1 ...
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... Zilog PIN DESCRIPTION 100 /INT1 1 /INT2 A15 A10 15 A11 A12 GND A13 A14 20 A16 /RAMCS 30 DS971800500 90 95 Z80181 100-Pin QFP Figure 2. 100-Pin QFP Pin Configuration PS009701-0301 MART CCESS ONTROLLER 85 80 /TEND1 /DREQ1 CKS RxS//CTS1 TxS 75 CKA1//TEND0 RxA1 TEST TxA1 ...
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... Zilog CPU SIGNALS Pin Name Pin Number Input/Output, Tri-State A19 - A0 4-17, 19-21, I/O, Active 1 64, 65, 91 D0-D7 22-29 I/O, Active 1 /RD 89 I/O, Active 0 /WR 88 I/O, Active 0 /MREQ 85 I/O, tri-state, Active 0 /IORQ 84 I/O, tri-state, Active 0 /M1 87 I/O, tri-state, Active 0 /RFSH 83 Out, tri-state, Active 0 ...
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... Zilog Pin Name Pin Number Input/Output, Tri-State /INT0 100 Wired-OR I/O, Active 0 /INT1 In, Active 0 /INT2 /NMI 99 In, Active 0 /HALT 81 Out, tri-state, Active 0 /BUSREQ 97 In, Active 0 /BUSACK 96 Out, Active 0 /WAIT 95 Wired-OR I/O, Active 0 DS971800500 Function Maskable Interrupt Request 0. Interrupt is generated by peripheral devices. This signal is accepted if the interrupt enable Flip-Flop (IFF) is set to “ ...
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... Zilog PERIPHERAL SIGNALS Pin Name Pin Number Input/Output, Tri-State RXA0, RXA1 70, 74 In, Active 1 TXA0, TXA1 69, 72 Out, Active 1 /RTS0 66 Out, Active 0 /DCD0 68 In, Active 0 /CTS0 67 In, Active 0 /CTS1/RXS 77 In, Active 0 CKA0//DREQ0 71 I/O, Active 1 CKA1//TEND0 75 I/O, Active 1 /TEND1 80 Out, Active 0 ...
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... Zilog SCC SIGNALS Pin Name Pin Number Input/Output, Tri-State /W//REQ 51 Active 0 /SYNC 50 I/O, Active 0 RxD 52 In, Active 1 /RTxC 49 In, Active 0 /TRxC 53 I/O, Active 0 DS971800500 Function Wait/Request. Open-drain when programmed for a Wait function, driven “1” or “0” when programming for a Re- quest function ...
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... Zilog SCC SIGNALS (Continued) Pin Name Pin Number Input/Output, Tri-State TxD 54 Out, Active 1 /DTR//REQ 55 Out, Active 0 /RTS 56 Out, Active 0 /CTS 57 In, Active 0 /DCD 58 In, Active 0 2-8 Function Transmit Data. This Output signal transmits serial data at standard TTL level. Data Terminal Ready/Request. This output follows the state programmed into the DTR bit ...
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... Zilog PIA/CTC SIGNALS Pin Name Pin Number Input/Output, Tri-State PIA17-PIA14 35-38 I/O PIA13-PIA10 31-34 I/O PIA27-20 41-48 I/O DS971800500 Function Port 1 Data 7-Port 1 Data 4 or CTC ZC/TO3 - ZC/TO0. These lines can be configured as inputs or outputs on a bit -by-bit basis. Also, under program control, these bits become Z80 CTC’ ...
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... Zilog SYSTEM CONTROL SIGNALS Pin Name Pin Number Input/Output, Tri-State ST 3 Out, Active 1 2-10 Function Status. This signal is used with the /M1 and /HALT output to decode the status of the CPU machine cycle. Note that the /M1 output is affected by the status of the M1E bit in the OMCR register ...
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... Zilog Pin Name Pin Number Input/Output, Tri-State IEI 62 In, Active 1 IEO 60 Out, Active 1 /ROMCS 61 Out, Active 0 /RAMCS 30 Out, Active 0 /RESET 98 In, Active 0 EXTAL 94 In, Active 1 XTAL 93 Out PHI 90 Out, Active Out, Active 1 TEST 73 Out V 39 18, 40, 59, SS 63, 92 DS971800500 Function Interrupt enable input signal. IEI is used with the IEO to form a priority daisy chain when there is more than one interrupt-driven peripheral ...
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... Zilog FUNCTIONAL DESCRIPTION Functionally, the on-chip Z181 MPU, SCC, and CTC are the same as the discrete devices (Figure 1). Therefore, refer to the Product Specification/Technical Manual of Timing Ø Generator 16-Bit Programmable A18 /TOUT Reload Timers (2) TxS Clocked Serial I/O RxS//CTS Port CKS ...
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... Zilog Z181 MPU This unit provides all the capabilities and pins of the Zilog Z180 MPU. Figure 3 shows the Z181 MPU block diagram. This allows 100% software compatibility with existing Z180 (and Z80) software. Note that the on-chip I/O address should not be relocated to the I/O address (from 0C0h to 0FFh) to avoid address conflicts ...
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... Zilog FUNCTIONAL DESCRIPTION (Continued) Internal Control Logic Interrupt Interrupt Control Control Lines Logic Z85C30 Serial Communication Controller Logic Unit This logic unit provides the user with a multi-protocol serial I/O channel that is completely compatible with the two channel Z85C30 SCC with the following exceptions: ...
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... Zilog Each of the Counter/Timer Channels, designated Chan- nels 0-3, have an 8-bit prescaler (when used in timer mode) and its own 8-bit counter to provide a wide range of count resolution. Each of the channels have their own Clock/Trigger input to quantify the counting process and an output to indicate zero crossing/timeout conditions. ...
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... Zilog FUNCTIONAL DESCRIPTION (Continued) Recommended characteristics of the crystal and the val- ues for the capacitor are as follows (the values will change with crystal frequency). Type of crystal: Fundamental, parallel type crystal (AT cut is recommended). Frequency tolerance: Application dependent. CL, Load capacitance: Approximately 22 pF (acceptable range is 20-30 pF) ...
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... Zilog PROGRAMMING (Continued) Table 1. I/O Control Register Address Address Register 00h Z181 MPU Control Registers to 3Fh (Relocatable to 040h-07Fh, or 080h-0BFh) E0h PIA1 Data Direction Register (P1DDR) E1h PIA1 Data Port (P1DP) E2h PIA2 Data Direction Register (P2DDR) E3h PIA2 Data Register (P2DP) ...
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... Zilog ASCI CHANNELS CONTROL REGISTERS CNTLA0 MPE Bit RE Upon RESET 0 0 R/W R/W R/W CNTLA1 Bit MPE RE Upon RESET 0 0 R/W R/W R/W 2-18 Addr 00h MPBR/ TE /RTS0 MOD2 MOD1 MOD0 EFR R/W R/W R/W R/W R/W R Start + 7-Bit Data + 1 Stop ...
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... Zilog CNTLB0 Bit MPBT MP Upon Reset Invalid 0 R/W R/W R/W † /CTS - Depending on the condition of /CTS pin Cleared to 0. General Divide Ratio (Divide Ratio = 10) SS (x16) 000 Ø 160 001 Ø 320 010 Ø 640 011 Ø 1280 100 Ø 2560 101 Ø ...
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... Zilog ASCI CHANNELS CONTROL REGISTERS (Continued) CNTLB1 /CTS/ Bit MPBT MP PS Upon Reset Invalid 0 R/W R/W R/W R/W General Divide Ratio (Divide Ratio = 10) SS (x16) 000 Ø 160 001 Ø 320 010 Ø 640 011 Ø 1280 100 Ø 2560 101 Ø ...
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... Zilog STAT0 Bit RDRF OVRN Upon Reset † /DCD †† /CTS STAT1 Bit RDRF OVRN Upon Reset DS971800500 Addr 04h PE FE RIE /DCD TDRE TIE † †† R R/W - Depending on the condition of /DCD Pin Pin TDRE 1 0 Figure 11. ASCI Status Register ...
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... Zilog ASCI CHANNELS CONTROL REGISTERS (Continued) TDR0 Write Only Addr 06h Transmit Data Figure 13. ASCI Transmit Data Register (Ch. 0) TDR1 Write Only Addr 07h Transmit Data Figure 14. ASCI Transmit Data Register (Ch. 1) CSI/O Registers CNTR Bit EF Upon Reset 0 R/W R SS2 Baud Rate 000 Ø ...
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... Zilog Figure 18. CSI/O Transmit/Receive Data Register TIMER REGISTERS Timer Data Registers TMDR0L Read/Write Addr 0Ch Figure 19. Timer 0 Data Register L TMDR1L Read/Write Addr 14h Figure 20. Timer 1 Data Register L Timer Reload Registers RLDR0L Read/Write Addr 0Eh Figure 23. Timer 0 Reload Register L DS971800500 TRDR Read/Write ...
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... Zilog Timer Reload Registers (Continued) RLDR0H Read/Write Addr 0Fh Figure 25. Timer 0 Reload Register H Timer Control Register TCR Bit TIF1 TIF0 Upon Reset TOC1,0 A15/TOUT 00 Inhibited 01 Toggle 10 11 Free Running Counter 2-24 8 Figure 26. Timer 1 Reload Register H Addr 10h TIE1 TIE0 TOC1 ...
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... Zilog DMA Registers SAR0L Read/Write Addr 20h SA7 SA0 SAR0H Read/Write Addr 21h SA15 SA8 SAR0B Read/Write Addr 22h SA19 SA16 - - - - Bits 0-2 (3) are used for SAR0B A19, A18, A17, A16 DMA Transfer Request /DREQ0 (external RDR0 (ASCI0 TDR0 (ASCI1 Not Used Figure 29 ...
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... Zilog DMA REGISTERS (Continued) BCR0L Read/Write Addr 26h BC7 BCR0H Read/Write Addr 27h BC15 Figure 31. DMA 0 Byte Counter Registers MAR1L Read/Write Addr 28h MA7 MAR1H Read/Write Addr 29h MA15 MAR1B Read/Write Addr 2Ah MA19 - - - - Figure 32. DMA 1 Memory Address Registers 2-26 BC0 BC8 Figure 33 ...
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... Zilog DSTAT Bit DE1 DE0 /DWE1 Upon Reset 0 0 R/W R/W R/W DMODE Bit - - Upon Reset 1 1 R/W DM1, 0 Destination MMOD 0 Cycle Steal Mode 1 Burst Mode DS971800500 Addr 30h /DWE0 DIE1 DIE0 - R/W R/W Figure 35. DMA Status Register Addr 31h DM1 ...
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... Zilog DMA REGISTERS (Continued) DCNTL Bit MWI1 MWI0 Upon Reset 1 1 R/W R/W R/W MWI1, 0 No. of Wait States DMSi 1 0 DM1 2-28 Addr 32h IWI1 IWI0 DMS1 DMS0 DIM1 R/W R/W R/W R/W R/W IWI1, 0 No. of Wait States Sense Edge Sense ...
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... Zilog MMU Registers CBR Bit CB7 CB6 Upon Reset 0 R/W R/W R/W BBR Bit BB6 BB7 Upon Reset 0 R/W R/W R/W CBAR Bit CA3 CA2 Upon Reset 1 1 R/W R/W R/W Figure 40. MMU Common/Bank Area Register DS971800500 CB5 CB4 CB3 CB2 ...
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... Zilog System Control Registers IL Bit IL7 IL6 Upon Reset 0 0 R/W R/W R/W ITC Bit TRAP UFO Upon Reset 0 0 R/W R/W R RCR Bit REFE REFW Upon Reset 1 1 R/W R/W R/W CYC1 2-30 Addr 33h IL5 - - - - R/W Figure 41. Interrupt Vector Low Register ...
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... Zilog OMCR Bit M1E /M1TE Upon Reset 1 R/W R/W W Note: This register has to be programmed as 0x0xxxxxb(x:don't care part of Initialization. Figure 44. Operation Mode Control Register ICR Bit IOA7 IOA6 Upon Reset 0 R/W R/W R/W DS971800500 /IOC - - - - R/W IOSTP - - - - R/W Figure 45. I/O Control Register ...
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... Zilog CTC Control Registers Channel Control Word This word sets the operating modes and parameters as described below. Bit D0 must be a “1” to indicate that this is a Control Word (Figure 46). This register has the following fields: Bit D7. Interrupt Enable. This bit enables the interrupt logic so that an internal INT is generated at zero count ...
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... Zilog Time Constant Word Before a channel can start counting, it must receive a time constant word. The time constant value may be anywhere between 1 and 256, with “0” being accepted as a count of 256 (Figure 47 Figure 47. CTC Time Constant Word SCC REGISTERS For more detailed information, please refer to the Z8030/ Z8530 SCC Technical Manual ...
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... Zilog SCC REGISTERS (Continued) Read Register (a) Read Register (b) Figure 49. SCC Read Register Bit Functions 2-34 Read Register Character Available Zero Count Tx Buffer Empty DCD Sync/Hunt CTS Tx Underrun/EOM Break/Abort * Modified if VIS bit in Write register 9 is set. Read Register All Sent Residue Code 2 ...
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... Zilog * Read Register Can only be accessed if the SDLC FIFO enhancement is enabled (WR15 bit D2 set to 1) (e) SDLC FIFO Status and Byte Count (LSB) * Read Register BC8 BC9 BC10 BC11 BC12 BC13 FDA: FIFO Available Status 1 Status Reads from FIFO FOS: FIFO Overflow Status ...
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... Zilog SCC REGISTERS (Continued) Read Register (i) Figure 49. SCC Read Register Bit Functions (Continued) Write Registers The SCC contains fifteen write registers that are pro- grammed to configure the operating modes of the chan- nel. With the exception of WR0, programming the write registers is a two step operation. The first operation is a ...
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... Zilog Write Register 0 (non-multiplexed bus mode Null Code Point High Reset Ext/Status Interrupts Send Abort (SDLC Enable Int on Next Rx Character Reset Tx Int Pending Error Reset Reset Highest IUS 0 0 Null Code 0 1 Reset Rx CRC Checker 1 0 Reset Tx CRC Generator 1 1 Reset Tx Underrun/EOM Latch ...
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... Zilog SCC REGISTERS (Continued) Write Register Write Register Sync Modes Enable Stop Bit/Character 1/2 Stop Bits/Character Stop Bits/Character 0 0 8-Bit Sync Character 0 1 16-Bit Sync Character 1 0 SDLC Mode (01111110 Flag External Sync Mode Clock Mode 0 1 X16 Clock Mode 1 0 X32 Clock Mode ...
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... Zilog Sync7 Sync6 Sync1 Sync0 Sync7 Sync6 Sync3 Sync2 ADR7 ADR6 ADR7 ADR6 Write Register Sync7 Sync6 Sync5 Sync4 Sync15 Sync14 Sync11 Sync10 0 1 Figure 50. Write Register Bit Functions (Continued) DS971800500 Write Register Sync5 Sync4 Sync3 Sync2 Sync1 Sync4 Sync3 Sync5 ...
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... Zilog SCC REGISTERS (Continued) Write Register Reset 0 1 Reserved 1 0 Channel Reset Force Hardware Reset (i) Write Register NRZ 0 1 NRZI 1 0 FM1 (Transition = FM0 (Transition = 0) (j) Figure 50. Write Register Bit Functions (Continued) 2-40 Write Register VIS NV DLC MIE Status High//Status Low ...
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... Zilog Write Register TC8 TC9 TC10 TC11 TC12 TC13 TC14 TC15 (m) Write Register Figure 50. Write Register Bit Functions (Continued) DS971800500 Write Register Upper Byte of Time Constant Null Command Enter Search Mode Reset Missing Clock Disable DPLL Set Source = BR Generator Set Source = /RTxC ...
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... Zilog PIA Control Registers PIA1 Data Direction Register (P1DDR, I/O Address E0h), PIA1 Data Port (P1DP, I/O address E1h), PIA2 Data Direc- tion Register (P2DDR, I/O Address E2h) and PIA2 Data Register (P2DP, I/O Address E3h). These four registers are E0H ...
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... Zilog REGISTERS FOR SYSTEM CONFIGURATION There are four registers to determine system configuration with the Z181. These registers are: RAM upper boundary address register (RAMUBR, I/O address EAh), RAM lower boundary address register (RAMLBR, I/O address EBh), ROM address boundary register (ROMBR, I/O address ECh) and System Configuration Register (SCR, I/O ad- dress EDh) ...
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... Zilog REGISTERS FOR SYSTEM CONFIGURATION (Continued) EDH 7 6 2-44 ECH Figure 57. ROM Boundary Register PIA1/CTIO 1 PIA1 Functions as CTC's I/O Pins 0 PIA1 Functions as I/O Port Reserved - Program as 0 ROM Emulator Mode (REME) 1 Data Bus in ROM Emulator Mode 0 Data Bus in Normal Mode Reserved - Program as 0 ...
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... Zilog System Configuration Register (I/O address EDh) This register is to determine the functionality of PIA1 and the Interrupt Daisy-Chain Configuration (Figure 13). This register has the following control bits: Bit D7. Reserved and should be programmed as “0”. Bit D6. Daisy-Chain Configuration. Determines the arrangement of the interrupt priority daisy chain. ...
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... Zilog Data Bus Direction Table 4 shows the state of the SAC’s data bus when in SAC bus master condition. Table 4. Data Bus Direction (Z181 Is Bus Master) I/O And Memory Transactions I/O I/O Write To Read From On-Chip On-Chip Peripherals Peripherals Peripheral Peripheral (SCC/CTC/ (SCC/CTC/ ...
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... Zilog Table 5 shows the state of the SAC’s data bus when the Z80181 is NOT in bus master condition. Table 5. Data Bus Direction for External Bus Master (Z80181 Is Not Bus Master) I/O And Memory Transactions I/O I/O Write To Read From On-Chip On-Chip Peripherals Peripherals Peripheral Peripheral ...
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... Zilog ABSOLUTE MAXIMUM RATINGS Voltage on V with respect to V ........... –0.3V to +7. Voltages on all inputs with respect to V ........................... –0. Storage Temperature ............................ – +150 C Operating Ambient Temperature ........................ See Ordering Information STANDARD TEST CONDITIONS The DC Characteristics and capacitance sections below apply for the following standard test conditions, unless otherwise noted ...
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... Zilog DC CHARACTERISTICS Z80181 Symbol Parameter V Input “H” Voltage IH1 /RESET, EXTAL, /NMI V Input “H” Voltage IH2 Except /RESET, EXTAL, /NMI V Input “L” Voltage IL1 /RESET, EXTAL, /NMI V Input “L” Voltage IL2 Except /RESET, EXTAL, /NMI V Output “H” Voltage OH All outputs ...
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... Zilog AC CHARACTERISTICS Z180 MPU Timing Figures 60-68 show the timing for the Z181 MPU and the referenced parameters appear in Table Ø Address /ROMCS /RAMCS /WAIT /MREQ /RD / "H" /IORQ /WR Data In 61 /RESET 67 2- Figure 60a. Opcode Fetch Cycle PS009701-0301 MART CCESS ONTROLLER ...
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... Zilog T1 Ø 6 Address 70 /ROMCS /RAMCS /WAIT 7 /IORQ 27 9 /RD 22 /WR Data IN Data OUT "H" ST [1] Output buffer is off at this point. [2] Memory Read/Write cycle timing is the same as this figure, except there is no automatic wait status (Twa), and /MREQ is active instead of /IORQ. Figure 60b. I/O Read/Write, Memory Read/Write Timing ...
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... Zilog AC CHARACTERISTICS (Continued) Z180 MPU Timing Ø /INTI 32 /NMI /INTSCC [4] /M1 [1] /IORQ [1] /Data IN [1] /MREQ [2] /RFSH [ /BUSREQ /BUSACK Address Data /MREQ, /RD, /WR, /IORQ /HALT Notes: [1] During /INT0 acknowledge cycle [2] During refresh cycle (/INT0 Acknowledge Cycle, Refresh Cycle, BUS RELEASE Mode HALT Mode, SLEEP Mode, SYSTEM STOP Mode) ...
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... Zilog I/O Read Cycle T1 T2 Ø Address 27 /IORQ 9 /RD /WR DS971800500 I/O Write Cycle Figure 62. CPU Timing (/IOC = 0) (I/O Read Cycle, I/O Write Cycle) PS009701-0301 MART CCESS ONTROLLER Z80181 SAC ™ 2-53 ...
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... Zilog AC CHARACTERISTICS (Continued) Z180 MPU Timing Ø /DREQi (At level sense) /DREQi (At edge sence) /TENDi ST DMA Control Signals [1] tDRQS and tDRQH are specified for the rising edge of clock followed by T3. [2] tDRQS and tDRQH are specified for the rising edge of clock. [3] DMA cycle starts. ...
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... Zilog T1 Ø E (Memory Read/Write) E (I/O Read) E (I/O Read) D7-D0 (Memory Read/Write Cycle, I/O Read/Write Cycle) Ø BUS RELEASE Mode E SLEEP Mode SYSTEM STOP Mode (BUS RELEASE Mode, SLEEP Mode, SYSTEM STOP Mode) DS971800500 (a) E Clock Timing 48 (b) E Clock Timing Figure 64. E Clock Timing ...
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... Zilog AC CHARACTERISTICS (Continued) Z180 MPU Timing T2 Ø E (Example: I/O Read - Op-code Fetch) E (I/O Write) (Minimum timing example of PWEL and PWEH) Ø A18/TOUT 2- Figure 65. E Clock Timing Timer Data Reg = 0000H 54 Figure 66. Timer Output Timing PS009701-0301 Z80181 ™ SAC MART CCESS ONTROLLER ...
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... Zilog SLP Instruction Fetch T3 T1 Ø /INTi /NMI A18-A0 /MREQ, /M1 /RD /HALT DS971800500 Figure 67. SLP Execution Cycle PS009701-0301 Z80181 SAC MART CCESS ONTROLLER Next Op-code Fetch 2-57 ™ ...
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... Zilog AC CHARACTERISTICS (Continued) Z180 MPU Timing CSI/O Clock Transmit Data (Internal Clock) Transmit Data (External Clock) Receive Data (Internal Clock) Receive Data (External Clock) Table A. Z180 CPU & 180 Peripherals Timing No Symbol Parameter 1 tcyc Clock Cycle Time 2 tCHW Clock Pulse Width (High) ...
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... Zilog Table A. Z180 CPU & 180 Peripherals Timing (Continued) No Symbol Parameter 11 tAH Address Hold Time (/MREQ, /IORQ, /RD, /WR) 12 tMED2 Clock Fall to /MREQ Rise Delay 13 tRDD2 Clock Fall to /RD Rise Delay 14 tM1D2 Clock Rise to /M1 Rise Delay 15 tDRS Data Read Setup Time ...
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... Zilog AC CHARACTERISTICS (Continued) ™ Z180 MPU Timing Table A. Z180 CPU &180 Peripherals Timing (Continued) No Symbol Parameter 47 tTED2 Clock Fall to /TENDi Rise Delay 48 tED1 Clock Rise to E Rise Delay 49 tED2 Clock Edge to E Fall Delay 50 PWEH E Pulse Width (High) 51 PWEL E Pulse Width (Low) ...
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... Zilog AC CHARACTERISTICS (Continued) CTC Timing Figure 69 shows the timing for the on-chip CTC. Param- eters referenced in this figure appear in Table B. Clock CLK/TRG Counter CLK/TRG Timer ZC/TO /INT No Symbol Parameter 1 TdCr(INTf) Clock Rise to /INT Fall Delay 2 TsCTRr(Cr)c CLK/TRG Rise to Clock Rise Setup Time for Immediate Count ...
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... Zilog AC CHARACTERISTICS (Continued) SCC Timing Figure 70 shows the AC characteristics for the on-chip SCC. Parameters referenced in this figure appear in Table C. Ø /WR /RD /W//REQ Wait /W//REQ Request /DTR//REQ Request /INT Table C. SCC Timing Parameters (85C30 AC Characteristics) No Symbol Parameter 1 TdWR(W) /WR Fall to Wait Valid Delay ...
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... Zilog Figure 71 shows the general timing for the on-chip SCC. Parameters referenced in this figure appear in Table D. PCLK /W//REQ Request /W//REQ Wait /RTxC, /TRxC Receive 3 RxD 7 /SYNC External /TRxC, /RTxC Transmit TxD /TRxC Output /RTxC /TRxC /CTS, /DCD /SYNC Input DS971800500 15, 21 ...
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... Zilog AC CHARACTERISTICS (Continued) SCC General Timing No Symbol Parameter 1 TdPC(REQ) Clock Fall to /W//REQ Valid 2 TdPC(W) Clock Fall to Wait Inactive 3 TsRXD(RXCr) RxD to /RxC Rise Setup Time 4 ThRXD(RXCr) RxD to /RxC Rise Hold Time 5 TsRXD(RXCf) RxD to /RxC Fall Setup Time 6 ThRXD(RXCf) RxD to /RxC Fall Hold Time ...
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... Zilog Figure 72 shows the system timing for the on-chip SCC. Parameters referenced in this figure appear in Table E. /RTxC, /TRxC Receive /W//REQ Request /W//REQ Wait /SYNC Output /INT /RTxC, /TRxC Transmit /W//REQ Request /W//REQ Wait /DTR//REQ Request /INT /CTS, /DCD /SYNC Input ...
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... Zilog AC CHARACTERISTICS (Continued) SCC System Timing No Symbol Parameter 1 TdRxC(REQ) /RxC to /W//REQ Valid 2 TdRxC(W) /RxC to Wait inactive 3 TdRxC(SY) /RxC to /SYNC Valid 4 TdRxC(INT) /RxC to /INT Valid 5 TdTxC(REQ) /TxC to /W//REQ Valid 6 TdTxC(W) /TxC to Wait inactive 7 TdRxC(DRQ) /TxC to /DTR//REQ Valid 8 TdTxC(INT) /TxC to /INT Valid ...
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... Zilog AC CHARACTERISTICS (Continued) PIA General-Purpose I/O Port Timing Figure 73 shows the timing for the PIA ports. Parameters referenced in this figure appear in Table F. Ø /IORQ, /RD PIA Input PIA Output Table F. PIA General-Purpose I/O Timing Parameters No Symbol Parameter 1 TsPIA(C) PIA Data Setup time to Clock Rise ...
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... Zilog AC CHARACTERISTICS (Continued) Interrupt Daisy-Chain Timing Figure 74 shows the interrupt daisy-chain timing. Parame- ters referenced in this figure appear in Table G. CLK 1 /M1 /IORQ Data IEI IEO 9 /INT (SCC) /WAIT Table G. Interrupt Daisy-Chain Timing Parameters No Symbol 1 TsM1(Cr) 2 TsM1(IO)INTA TdM1r(DOz) 5 TdCr(DO) 6 TsIEI(TW4) 7 TdIEIf(IEOf) 8 TdIEIr(IEOr) ...
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... Zilog Note for Interrupt Acknowledge Cycle and Daisy Chain When using the interrupt daisy chained device(s) for other than the Z181 (without external logic), the following restric- tions/notes apply: The device(s) must be connected to the higher priority location (Figure 75). The device(s) IEI-IEO delay must be less than two clock cycles ...
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... Zilog AC CHARACTERISTICS (Continued) Read Write External BUS Master Timing CLK Address A7-A0 /IORQ /RD Data /WR Data Figure 76. Read/Write External BUS Master Timing Table H. External Bus Master Interface Timing (Read/Write Cycles) No Symbol 1 TsA(Cr) 2 TsIO(Cr TsRD(Cr) 5 TdRD(DO) 6 TdRIr(DOz) 7 TsWR(Cr) 8 TsDi(WRf) 9 ThWIr(Di) 10 TsA(IORQf) 11 TsA(RDf) 12 TsA(WRf) ...
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... Zilog SCC External BUS Master Timing Valid SCC Addr * IORQ /RD or /WR DTR/REQ Request Figure 77. SCC External BUS Master Timing Table I. External Bus Master Interface Timing (SCC Related Timing) No Symbol Parameter 1 TrC Valid Access Recovery Time 2 TdRDr(REQ) /RD Rise to /DTR//REQ Not Valid Delay Note for Table I: [1] Only applies between transactions involving the SCC ...
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... Zilog AC CHARACTERISTICS (Continued CLK /M1 /IORQ SCC /INTACK /WAIT SCC /RD CTC /IORQ Figure 78. Interrupt Acknowledge Cycle Timing Vcc IEI CTC Figure 79. Peripheral Device as Part of the Daisy Chain 2- Settle Time for Settle Time for Off-chip Z80 On-chip CTC Peripherals Settle Time for SCC ...
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... Zilog PACKAGE INFORMATION DS971800500 100-Pin QFP Package Diagram PS009701-0301 Z80181 SAC ™ MART CCESS ONTROLLER 2-73 ...
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... Zilog ORDERING INFORMATION Z80181 (10 MHz) Extended Temperature 100-Pin QFP Z8018110FEC Package Longer Lead Time F = Plastic Quad Flat Pack Temperature Longer Lead Time E = – +100 C Environmental C = Plastic Standard Speed MHz Example: Z 80181 Z80181, 10 MHz, QFP, – +100 C, Plastic Standard Flow Environmental Flow ...