Z8018110FEC Zilog, Z8018110FEC Datasheet - Page 14

• Manufacturer Part Number: Z8018110FEC
• Description: IC 10MHZ ACCESS CTRL 100-QFP
• Manufacturer: Zilog

Specifications of Z8018110FEC

• Processor Type: Z180
• Features: Smart Access Controller SAC™
• Speed: 10MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Zilog
FUNCTIONAL DESCRIPTION (Continued)
Z85C30 Serial Communication Controller
Logic Unit
This logic unit provides the user with a multi-protocol serial
I/O channel that is completely compatible with the two
channel Z85C30 SCC with the following exceptions:
Their basic functions as serial-to-parallel and parallel-to-
serial converters can be programmed by the CPU for a
broad range of serial communications applications. This
logic unit is capable of supporting all common asynchro-
nous and synchronous protocols (Monosync, Bisync, and
SDLC/HDLC, byte or bit oriented - Figure 4).
On the discrete version of the SCC (dual channel version),
there are two registers shared between channels A and B,
and two registers whose functions are different by chan-
nel. These are: WR2, WR9 (shared registers), and RR2 and
RR3 (different functionality).
Following are the differences in functionality:
2-14
RR2 - Returns Unmodified Vector or modified vector
depends on the status of “VIS” (Vector Include Status)
bit in WR9.
Interrupt
Control
Lines
Interrupt
Internal
Control
Control
Logic
Logic
Baud Rate
Generator
Registers
Channel
Internal BUS
Figure 4. SCC Block Diagram
PS009701-0301
10 X 19
Frame
Status
FIFO
The PCLK for the SCC is connected to PHI (System clock),
the /INT signal is connected to /INT0 signal internally
(requires external pull-up resistor) and SCC is reset when
/RESET input becomes active. Interrupt from the SCC is
handled through Mode 2 interrupt. During the interrupt
acknowledge cycle, the on-chip SCC interface circuit
inserts two wait states automatically.
Z84C30 Counter/Timer Logic Unit
This logic unit provides the user with four individual 8-bit
Counter/Timer Channels that are compatible with the
Z84C30 CTC (Figure 5). The Counter/Timers are pro-
grammed by the CPU for a broad range of counting and
timing applications. Typical applications include event
counting, interrupt and interval counting, and serial baud
rate clock generation.
RR3 - Returns IP status (Ch.A side).
WR9 - Ch.B Software Reset command has no effect.
Channel
Discrete
& Status
Control
S
/SYNC
/Wait
} Serial Data
} Channel Clocks
MART
Modem, DMA,
or Other
Controls
A
CCESS
C
DS971800500
ONTROLLER
Z80181
SAC
™