MC68360EM25VL Freescale Semiconductor, MC68360EM25VL Datasheet - Page 553
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MC68360EM25VL
Manufacturer Part Number
MC68360EM25VL
Description
IC MPU QUICC 25MHZ 240-FQFP
Manufacturer
Freescale Semiconductor
Datasheets
1.MC68EN360VR25L.pdf
(14 pages)
2.MC68EN360VR25L.pdf
(2 pages)
3.MC68360AI25L.pdf
(962 pages)
Specifications of MC68360EM25VL
Processor Type
M683xx 32-Bit
Speed
25MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
240-FQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC68360EM25VL
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MC68360EM25VL
Manufacturer:
MOTOROLA/摩托罗拉
Quantity:
20 000
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Bits 14, 10, 8, 6, 5, 3—Reserved
W—Wrap (Final BD in Table)
I—Interrupt
L—Last in Frame
F—First in Frame
CM—Continuous Mode
DE—DPLL Error
NO—Rx Nonoctet Aligned Frame
This bit is set by the transparent controller when this buffer is the last in a frame. This im-
plies the negation of CD in envelope mode or the reception of an error, in which case one
or more of the OV, CD, and DE bits are set. The transparent controller will write the num-
ber of frame octets to the data length field.
This bit is set by the transparent controller when this buffer is the first in a frame.
This bit is set by the transparent controller when a DPLL error has occurred during the
reception of this buffer. In Decoding modes where a transition is promised every bit, the
DPLL error will be set when a missing transition occurs.
A frame that contained a number of bits not exactly divisible by eight was received.
1 = The data buffer associated with this BD is empty, or reception is currently in
0 = This is not the last BD in the Rx BD table.
1 = This is the last BD in the Rx BD table. After this buffer has been used, the CP will
0 = No interrupt is generated after this buffer has been used.
1 = When this buffer has been closed by the transparent controller, the RX bit in the
0 = This buffer is not the last in a frame.
1 = This buffer is the last in a frame.
0 = The buffer is not the first in a frame.
1 = The buffer is the first in a frame.
0 = Normal operation.
1 = The E-bit is not cleared by the CP after this BD is closed, allowing the associated
progress. This Rx BD and its associated receive buffer are owned by the CP. Once
the E-bit is set, the CPU32+ core should not write any fields of this Rx BD.
receive incoming data into the first BD in the table (the BD pointed to by RBASE).
The number of Rx BD s in this table is programmable and is determined only by
the W-bit and the overall space constraints of the dual-port RAM.
transparent event register will be set. The RX bit can cause an interrupt if it is en-
abled.
data buffer to be overwritten automatically when the CP next accesses this BD.
However, the E-bit will be cleared if an error occurs during reception, regardless of
the CM bit.
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
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