MC68360EM25VL Freescale Semiconductor, MC68360EM25VL Datasheet - Page 89
MC68360EM25VL
Manufacturer Part Number
MC68360EM25VL
Description
IC MPU QUICC 25MHZ 240-FQFP
Manufacturer
Freescale Semiconductor
Datasheets
1.MC68EN360VR25L.pdf
(14 pages)
2.MC68EN360VR25L.pdf
(2 pages)
3.MC68360AI25L.pdf
(962 pages)
Specifications of MC68360EM25VL
Processor Type
M683xx 32-Bit
Speed
25MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
240-FQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC68360EM25VL
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MC68360EM25VL
Manufacturer:
MOTOROLA/摩托罗拉
Quantity:
20 000
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Figure 4-8 shows the transfer of a long-word operand to an odd address in word-organized
memory, which requires three bus cycles. For the first cycle, the SIZx signals specify a long-
word transfer, and the address offset (A2–A0) is 001. Since the port width is 16 bits, only the
first byte of the long word is transferred. The slave device latches the byte and acknowl-
edges the data transfer, indicating that the port is 16 bits wide. When the processor starts
the second cycle, the SIZx signals specify that three bytes remain to be transferred with an
address offset (A2–A0) of 010. The next two bytes are transferred during this cycle. The pro-
cessor then initiates the third cycle, with the SIZx signals indicating one byte remaining to
be transferred. The address offset (A2–A0) is now 100; the port latches the final byte, and
the operation is complete. Figure 4-9 shows the associated bus transfer signal timing.
Figure 4-7. Word Operand Write Timing (8-Bit Data Port)
FC3–FC0
D31–D24
D23–D16
DSACK0
DSACK1
D15–D8
A31–A2
CLKO1
D7–D0
SIZ0
SIZ1
R/W
DS
AS
A0
A1
Freescale Semiconductor, Inc.
For More Information On This Product,
S0
MC68360 USER’S MANUAL
Go to: www.freescale.com
BYTE WRITE
S2
OP3
OP2
OP2
OP3
WORD OPERAND WRITE
S4
S0
BYTE WRITE
S2
OP3
OP3
OP3
OP3
S4
Bus Operation
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