MC68MH360EM25L Freescale Semiconductor, MC68MH360EM25L Datasheet - Page 386

• Manufacturer Part Number: MC68MH360EM25L
• Description: IC MPU QUICC ETHER 25MHZ 240FQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360EM25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

Serial Interface with Time Slot Assigner
7.8 SERIAL INTERFACE WITH TIME SLOT ASSIGNER
The SI connects the physical layer serial lines to the four SCCs and two SMCs (see Figure
7-19). In its simplest configuration, the SI allows the four SCCs and two SMCs to be con-
nected their own set of individual pins. Each SCC or SMC that connects to the external world
in this way is said to connect to an NMSI. In the NMSI configuration, the SI provides a flexible
clocking assignment for each SCC and SMC from a bank of external clock pins and/or inter-
nal baud rate generators.
However, the main feature of the SI is its TSA. The TSA allows any combination of SCCs
and SMCs to multiplex their data together on either one or two TDM channels. TDM is used
in this manual as the generic term that describes any serial channel that is divided into chan-
nels separated by time. Common examples of TDMs are the T1 lines in Japan and the
United States and the CEPT lines in Europe.
Even if the TSA is not used in its intended capacity, it may still be used to generate complex
waveforms on four output pins. For instance, these pins can be programmed by the TSA to
implement stepper motor control or variable duty cycle and period control on these pins. Any
programmed configuration may be changed on the fly.
7.8.1 SI Key Features
The two major features of the SI are the TSA and the NMSI. The TSA contains the following
features:
7-62
• Can Connect to Two Independent TDM channels. Each TDM May Be One of the Fol-
• Independent, Programmable Transmit and Receive Routing Paths
• Independent Transmit and Receive Frame Syncs Allowed
• Independent Transmit and Receive Clocks Allowed
• Selection of Rising/Falling Clock Edges for the Frame Sync and Data Bits
• Supports 1 and 2 Input Clocks (i.e., 1 or 2 Clocks per Data Bit)
• Selectable Delay (0–3 Bits) Between Frame Sync and Frame Start
• Four Programmable Strobe Outputs and Two (2 ) Clock Output Pins
• 1- or 8-Bit Resolution in Routing, Masking, and Strobe Selection
• Supports Frames Up to 8192 Bits Long
• Internal Routing and Strobe Selection Can Be Dynamically Programmed
• Supports Automatic Echo and Loopback Mode for Each TDM
lowing:
—T1 or CEPT Line
—PCM Highway
—ISDN Primary Rate
—ISDN Basic Rate—IDL
—ISDN Basic Rate—GCI
—User-Defined Interfaces
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
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