MC68MH360EM25L Freescale Semiconductor, MC68MH360EM25L Datasheet - Page 470

• Manufacturer Part Number: MC68MH360EM25L
• Description: IC MPU QUICC ETHER 25MHZ 240FQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360EM25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

Freescale Semiconductor, Inc.
Serial Communication Controllers (SCCs)
IDLC. This value is used by the RISC to store the current idle counter value in the MAX_IDL
timeout process. IDLC is a down-counter; it does not need to be initialized or accessed by
the user.
BRKCR. The UART controller will send an a break character sequence whenever a STOP
TRANSMIT command is given. The number of break characters sent by the UART controller
is determined by the value in BRKCR. In the case of 8 data bits, no parity, 1 stop bit, and 1
start bit, each break character is 10 bits in length and consists of all zeros.
16
) counters are initialized
PAREC, FRMEC, NOSEC, and BRKEC. These 16-bit (modulo–2
by the user. When the associated condition occurs, they will be incremented by the RISC
controller. PAREC counts received parity errors. FRMEC counts received characters with
framing errors. NOSEC counts received characters with noise errors (one of the three sam-
ples was different). BRKEC counts the number of break conditions that occurred on the line.
Note that one break condition may last for hundreds of bit times, yet this counter is incre-
mented only once during that period.
BRKLN. This value is used to store the length of the last break character received. This
value is the length in characters of the break. Example: If the receive pin is low for 20 bit
times, BRKLN will show the value $0010. BRKLN is accurate to within one character unit of
bits. For example, for 8 data bits, no parity, 1 stop bit, and 1 start bit, BRKLN is accurate to
within 10 bits.
UADDR1, UADDR2. In the multidrop mode, the UART controller can provide automatic
address recognition of two addresses. In this case, the lower order bytes of UADDR1 and
UADDR2 are programmed by the user with the two desired addresses.
TOSEQ. This value is used to transmit out-of-sequence characters in the transmit stream
such as the XOFF and XON characters. Using this field, the desired characters can be
inserted into the transmit FIFO without affecting any transmit buffer that might currently be
in progress.
CHARACTER1–8. These characters define the receive control characters on which inter-
rupts may be generated.
RCCM. This value is used to mask the comparison of CHARACTER1–8 so that classes of
control characters may be defined. A one enables the bit comparison, a zero masks it.
RCCR. This value is used to hold the value of any control character that is NOT to be written
to the data buffer.
RLBC. This entry is used in synchronous UART, when the RZS bit is set in the PSMR. This
entry contains the actual pattern of the last break character. By counting the zeros in this
entry, the CPU32+ core can measure the break length to a bit resolution. The user reads
RLBC by counting the number of zeros written, starting at bit 15 down to the point where the
first one is written. Therefore, RLBC = 001xxxxxxxxxxxxx (binary) indicates two zeros, and
RLBC = 1xxxxxxxxxxxxxxx (binary) indicates no zeros.
7-146
MC68360 USER’S MANUAL
MOTOROLA
For More Information On This Product,
Go to: www.freescale.com