MC68MH360EM25L Freescale Semiconductor, MC68MH360EM25L Datasheet - Page 496

• Manufacturer Part Number: MC68MH360EM25L
• Description: IC MPU QUICC ETHER 25MHZ 240FQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360EM25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

Serial Communication Controllers (SCCs)
7.10.17.3 HDLC CHANNEL FRAME RECEPTION PROCESSING. The HDLC receiver is
also designed to work with almost no intervention from the CPU32+ core. The HDLC
receiver can perform address recognition, CRC checking, and maximum frame length
checking. The received frame is available to the user for performing any HDLC-based pro-
tocol.
When the CPU32+ core enables one of the receivers, the receiver waits for an opening flag
character. When the receiver detects the first byte of the frame, the HDLC controller will
compare the frame address against the user-programmable addresses. The user has four
16-bit address registers and an address mask available for address matching. The HDLC
controller will compare the received address field to the user-defined values after masking
with the address mask. The HDLC controller can also detect broadcast (all ones) address
frames, if one address register is written with all ones.
If a match is detected, the HDLC controller will fetch the next BD and, if it is empty, will start
to transfer the incoming frame to the BD’s associated data buffer. When the data buffer has
been filled, the HDLC controller clears the E-bit in the BD and generates an interrupt if the
I-bit in the BD is set. If the incoming frame exceeds the length of the data buffer, the HDLC
controller will fetch the next BD in the table and, if it is empty, will continue to transfer the
rest of the frame to this BD’s associated data buffer.
During this process, the HDLC controller will check for a frame that is too long. When the
frame ends, the CRC field is checked against the recalculated value and is written to the
data buffer. The data length written to the last BD in the HDLC frame is the length of the
entire frame. This enables HDLC protocols that “lose” frames to correctly recognize the
frame-too-long condition. The HDLC controller then sets the last buffer in frame bit, writes
the frame status bits into the BD, and clears the E-bit. The HDLC controller next generates
a maskable interrupt, indicating that a frame has been received and is in memory. The
HDLC controller then waits for a new frame. Back-to-back frames may be received with only
a single shared flag between frames.
The user can configure the HDLC controller not to interrupt the CPU32+ core until a certain
number of frames has been received. This is configured in the received frames threshold
(RFTHR) location of the parameter RAM. The user can combine this function with a timer to
implement a timeout if less than the threshold number of frames is received.
7.10.17.4 HDLC MEMORY MAP. When configured to operate in HDLC mode, the QUICC
overlays the structure listed in Table 7-5 with the HDLC-specific parameters described in
Table 7-8.
7-172
SCC Base + 30
SCC Base + 34
SCC Base + 38
SCC Base + 3C
SCC Base + 3E
Address
Freescale Semiconductor, Inc.
Table 7-8. HDLC-Specific Parameters
For More Information On This Product,
C_MASK
C_PRES
CRCEC
DISFC
Name
RES
MC68360 USER’S MANUAL
Go to: www.freescale.com
Width
Word
Word
Long
Long
Long
Reserved
CRC Constant
CRC Preset
Discard Frame Counter
CRC Error Counter
Description
MOTOROLA