MC68MH360EM25L Freescale Semiconductor, MC68MH360EM25L Datasheet - Page 784

• Manufacturer Part Number: MC68MH360EM25L
• Description: IC MPU QUICC ETHER 25MHZ 240FQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360EM25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

Applications
After determining what caused the interrupt, the service routine would branch to the appro-
priate portion of the program to execute. IRQ2 was chosen to cause the 53C90 interrupts to
have a lower priority than interrupts from other high-speed serial activity. The priority can be
moved up if the system requires it.
9.6.5.5 IDMA1 SETUP AND TIMING. After the processor initializes the 53C90 and all its
registers, IDMA1 will take care of all the data movement to and from memory. The 53C90
has a DMA interface, and special care should be taken in the hardware connections. Chip
select and DACK cannot be asserted at the same time on the 53C90. When IDMA1 is
requested, it will put out the address of the 53C90 and assert the chip select. To overcome
this, another chip select is used with a different address range. The 53C90 needs the mini-
mum memory range available (2K block). Assuming all peripherals are at address
$04000000 and the 53C90 is at address $04001000, then CS7 will decode $04001000 on
the read/write cycles, and CS6 will decode $04001800 on the DMA cycles. This way the
53C90 will take a 4K address block. CS6 is used because it will provide DSACK1 to termi-
nate the DMA cycles.
The 53C90 requires DACK to be cycled once for each DMA access. This is available on the
QUICC for both single and dual address transfers. In this case, however, packing of data
from the 8-bit SCSI port to a 32-bit memory is desired; therefore, dual address transfers
must be used. Thus, the SCSI will be accessed four times followed by a 32-bit access to
memory. The maximum transfer rate in this case is 7.1 Mbyte/sec:
(4 byte
Accesses to the 53C90 are three clocks; whereas, memory may be accessed as fast as two
clocks.
IDMA1 has eight registers that define its specific operation:
These registers provide the addresses, transfer count, and configuration information neces-
sary to set up a transfer. They also provide a means of controlling the IDMA channel and
monitoring its status. All registers can be modified by the CPU32+ core. The data holding
register is another 32-bit register in the IDMA, but it is not accessible by the CPU32+ core.
It is used for temporary data storage.
Every IDMA operation involves the following steps: channel initialization, data transfer and
block termination. In the initialization phase, the CPU32+ loads the registers with control
information, then starts the channel. In the transfer phase, the IDMA accepts requests for
operand transfers and provides addressing and bus control for the transfers. The termina-
tion phase occurs when the transfer is complete and the IDMA interrupts the CPU32+.
9-64
32-Bit Source Address Pointer Register (SAPR)
32-Bit Destination Address Pointer Register (DAPR)
16-Bit Channel Configuration Register (ICCR)
8-Bit Channel Mask Register (CMAR)
8-Bit Function Code Register (FCR)
32-Bit Byte Count Register (BCR)
8-Bit Channel Status Register (CSR)
32-Bit Channel Mode Register (CMR)
25 Mclocks/sec) / ((4
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3) + 2 clocks per transfer) = 7.1 Mbyte/sec
MC68360 USER’S MANUAL
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