MPC180LMB Freescale Semiconductor, MPC180LMB Datasheet - Page 56

• Manufacturer Part Number: MPC180LMB
• Description: IC SECURITY PROCES 66MHZ 100LQFP
• Manufacturer: Freescale Semiconductor

Specifications of MPC180LMB

• Processor Type: Security Processor
• Speed: 66MHz
• Voltage: 1.8V
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

Freescale Semiconductor, Inc.
Operational Registers
7.1.5 EXP(k) Register
The EXP(k) register contains the exponent (EXP) during exponentiation routines or the
point multiplier (k) during ECC point multiply routines. EXP(k)_SIZE must be specified
before writing to the EXP(k) register. Since EXP(k) is 32 bits in size, data must be written
to it during exponentiations or point multiplies and never before. This data must be
provided most significant word (msw) to least significant word (lsw). The host processor
determines, via IRQ (if not masked) or IRDY (if selected to send via a DREQ pin), that new
data is required. When IRQ is asserted, the host processor will look at the status word to see
what was set. If the E(k) RDY bit is set, the host processor knows it must provide the next
byte of EXP(k). If IRQ is masked, then it must poll the status register to determine when to
provide the next word of EXP(k). When the host writes to the EXP(k) register, the E(k)
RDY bit of the status register is cleared. As with all status register bits, the writing to the
status register location will clear all of its bits, including the E(k) RDY bit.
There is an associated latency between the writing of the EXP(k) register and the
deassertion of E(k) RDY (and IRQ). For this reason, it is recommended that the host waits
a minimum of three cycles before polling the status register following a write to EXP(k).
The EXP(k) register is internally double-buffered. As a result, the host response time, while
important, is not critical to meet maximum performance. At a minimum, the host will have
32 integer multiplies for RSA or 32 point doubles for ECC to provide new data before
adversely impacting the run time. Refer to the run-time formulae (see Table 7-26) to
determine the exact time available for the target operating frequency.
The host will be required to provide the first byte of EXP(k) very shortly after initiating the
routine (point multiply or exponentiation). Because of the double buffering, the second byte
will be allowed to be written very shortly after the first written byte of EXP(k). For this
reason, IRQ and E_RDY is deasserted for only one cycle following the write of the first byte
of EXP(k). Once the second byte of EXP(k) is written, then there is a larger amount of time
before the subsequent IRQ and E_RDY is asserted.
The maximum size for either the exponent or k is limited only by the EXP(k)_SIZE register
that is, 64 words or 2048 bits). In practice, the values are typically less than or equal to the
key size (for RSA) or field size (ECC).
7.1.6 Program Counter Register (PC)
The Program Counter is an 11-bit register that contains the address of the next instruction
to be executed. This register is a read-write register. During normal routine execution, this
register is preloaded with the software routine’s entry address.
7-6
MPC180LMB Security Processor User’s Manual
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