MPC7410RX500LE Freescale Semiconductor, MPC7410RX500LE Datasheet - Page 28

• Manufacturer Part Number: MPC7410RX500LE
• Description: IC MPU 32BIT 500MHZ PPC 360-CBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC7410RX500LE

• Processor Type: MPC74xx PowerPC 32-Bit
• Speed: 500MHz
• Voltage: 1.8V
• Mounting Type: Surface Mount
• Package / Case: 360-FCCBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

Pinout Listings
28
V
Notes:
1. OV DD supplies power to the processor bus, JTAG, and all control signals except the L2 cache controls (L2CE, L2WE, and
2. These are test signals for factory use only and must be pulled up to OV
3. To allow for future I/O voltage changes, provide the option to connect BVSEL and L2VSEL independently to either OV
4. PLL_CFG[0:3] must remain stable during operation; should only be changed during the assertion of HRESET or during sleep
5. Ignored input in 60x bus mode.
6. Unused output in 60x bus mode. Signal is three-stated in 60x mode.
7. Deasserted (pulled high) at HRESET negation for 60x bus mode. Asserted (pulled low) at HRESET negation for MPX bus
8. Uses one of nine existing no connects in the MPC750 360 BGA package.
9. Internal pull up on die. Pulled-up signals are V
10.Reuses MPC750 DRTRY, DBDIS, and TLBISYNC pins (DTI1, DTI2, and EMODE, respectively).
11.The VOLTDET pin position on the MPC750 360 BGA package is now an L2OV
12.Output only for MPC7410, was I/O for MPC750.
13.MPX bus mode only.
14.If necessary, to overcome the internal pull-up resistance and ensure this input will recognize a low signal, a pull-down
15.MCP minimum pulse width: asynchronous, falling-edge input needs to be held asserted for a minimum of 2 cycles to
16.In MPX bus mode the ABB signal is called AMON and the DBB signal is called DMON. These signals are not a requirement
Signal Name
DD
L2ZZ); L2OV
and the L2 control signals; and V
AV
as selected by the BVSEL/L2VSEL pin configurations of
of V
GND, HRESET, or ¬HRESET. For the MPC7410 the L2 bus only supports 2.5- and 1.8-V options. The default selection, if
L2VSEL is left unconnected, is 2.5-V operation. For the MPC7410 the processor bus supports 3.3-, 2.5-, and 1.8-V options.
The default selection, if BVSEL is left unconnected, is 3.3-V operation. Refer to
settings.
mode and must adhere to the internal PLL-relock time requirement.
mode.
resistance less than 250 Ω should be used.
guarantee that it is latched by the processor.
of the MPX bus protocol and may not be available on future products.
DD
in
Table 12. Pinout Listing for the MPC7410, 360 CBGA and 360 HCTE Packages (continued)
and L2AV
or supply voltages, see
DD
G8, G10, G12, J8, J10, J12, L8, L10, L12, N8, N10, N12
DD
supplies power to the L2 cache interface (L2ADDR[0:18], L2DATA[0:63], L2DP[0:7], and L2SYNC_OUT)
, respectively). These columns serve as a reference for the nominal voltage supported on a given signal
MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1
Table
DD
3.
supplies power to the processor core and the PLL and DLL (after filtering to become
Pin Number
DD
based.
Table 2
and the voltage supplied. For actual recommended value
DD
for normal machine operation.
Active
—
DD
Table 2
pin on the MPC7410 360 package.
for supported BVSEL and L2VSEL
I/O
—
Freescale Semiconductor
I/F Select
N/A
1
Notes
—
DD
,