MC68HC000EI10 Freescale Semiconductor, MC68HC000EI10 Datasheet - Page 19

• Manufacturer Part Number: MC68HC000EI10
• Description: IC MPU 16BIT 10MHZ 68-PLCC
• Manufacturer: Freescale Semiconductor

Specifications of MC68HC000EI10

• Processor Type: M680x0 32-Bit
• Speed: 10MHz
• Voltage: 3.3V, 5V
• Mounting Type: Surface Mount
• Package / Case: 68-PLCC
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 16/32Bit
• Frequency (max): 10MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 68
• Package Type: PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

2.3
The eight data registers support data operands of 1, 8, 16, or 32 bits. The seven address
registers and the active stack pointer support address operands of 32 bits.
2.3.1 Data Registers
Each data register is 32 bits wide. Byte operands occupy the low-order 8 bits, word
operands the low-order 16 bits, and long-word operands, the entire 32 bits. The least
significant bit is addressed as bit zero; the most significant bit is addressed as bit 31.
MOTOROLA
DATA ORGANIZATION IN REGISTERS
NOTES: 1. The VBR, SFC, and DFC apply to the MC68010 only
Register Direct Addressing
Absolute Data Addressing
Program Counter Relative
Addressing
Register Indirect Addressing
Immediate Data Addressing
Implied Addressing 1
Data Register Direct
Absolute Long
Immediate
Quick Immediate
Implied Register
Address Register Direct
Absolute Short
Relative with Offset
Relative with Index and Offset
Register Indirect
Postincrement Register Indirect
Predecrement Register Indirect
Register Indirect with Offset
Indexed Register Indirect with Offset
M68000 8-/16-/32-BIT MICROPROCESSOR USER’S MANUAL
EA
Dn
An
( )
PC
d 8
d 16 =
N
¯
Xn
SR
USP =
SSP =
CP
VBR =
Freescale Semiconductor, Inc.
=
=
=
=
=
=
=
=
=
=
=
For More Information On This Product,
Table 2-1. Data Addressing Modes
Effective Address
Data Register
Address Register
Contents of
Program Counter
8-Bit Offset (Displacement)
16-Bit Offset (Displacement)
1 for byte, 2 for word, and 4 for long word. If An is the stack pointer and
the operand size is byte, N = 2 to keep the stack pointer on a word boundary.
Replaces
Address or Data Register used as Index Register
Status Register
User Stack Pointer
Supervisor Stack Pointer
Program Counter
Vector Base Register
Mode
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EA = SR, USP, SSP, PC,
EA=Dn
EA=An
EA = (Next Word)
EA = (Next Two Words)
EA = (PC)+d 16
EA = (PC)+d 8
EA = (An)
EA = (An), An
An
EA = (An)+d 16
EA = (An)+(Xn)+d 8
DATA = Next Word(s)
Inherent Data
¯
An–N, EA=(An)
Generation
VBR, SFC, DFC
An+N
Dn
An
(xxx).W
(xxx).L
(d 16 ,PC)
(d 8 ,PC,Xn)
(An)
(An)+
-(An)
(d 16 ,An)
(d 8 ,An,Xn)
#<data>
SR,USP,SSP,PC,
VBR, SFC,DFC
S y n t a x
2-5