ATF20V8B-15PC Atmel, ATF20V8B-15PC Datasheet - Page 5

• Manufacturer Part Number: ATF20V8B-15PC
• Description: IC PLD 15NS 24DIP
• Manufacturer: Atmel

Specifications of ATF20V8B-15PC

• Programmable Type: EE PLD
• Number Of Macrocells: 8
• Voltage - Input: 5V
• Speed: 15ns
• Mounting Type: Through Hole
• Package / Case: 24-DIP (0.300", 7.62mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: ATF20V8B15PC

Input Test Waveforms and
Measurement Levels
t
Pin Capacitance
f = 1 MHz, T = 25°C
Note:
Power-up Reset
The registers in the ATF20V8Bs are designed to reset dur-
ing power-up. At a point delayed slightly from V
V
the registered output state will always be high on power-up.
This feature is critical for state machine initialization. How-
ever, due to the asynchronous nature of reset and the
uncertainty of how V
lowing conditions are required:
1. The V
2. After reset occurs, all input and feedback setup
3. The clock must remain stable during t
Preload of Registered Outputs
The ATF16V8B’s registers are provided with circuitry to
allow loading of each register with either a high or a low.
This feature will simplify testing since any state can be
forced into the registers to control test sequencing. A
JEDEC file with preload is generated when a source file
with vectors is compiled. Once downloaded, the JEDEC file
preload sequence will be done automatically by most of the
approved programmers after the programming.
Electronic Signature Word
There are 64 bits of programmable memory that are always
available to the user, even if the device is secured. These
bits can be used for user-specific data.
R
C
C
RST
, t
IN
OUT
F
times must be met before driving the clock pin high,
and
, all registers will be reset to the low state. As a result,
< 5 ns (10% to 90%)
1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested.
CC
rise must be monotonic,
(1)
CC
actually rises in the system, the fol-
Typ
5
6
PR
.
CC
Max
crossing
8
8
Output Test Loads
Commercial
Security Fuse Usage
A single fuse is provided to prevent unauthorized copying
of the ATF20V8B fuse patterns. Once programmed, fuse
verify and preload are inhibited. However, the 64-bit User
Signature remains accessible.
The security fuse should be programmed last, as its effect
is immediate.
Programming/Erasing
Programming/erasing is performed using standard PLD
programmers. For further information, see the Configurable
Logic Databook, section titled, “CMOS PLD Programming
Hardware and Software Support.”
Parameter
t
V
PR
RST
Units
pF
pF
Description
Power-up Reset Time
Power-up Reset Voltage
Conditions
V
V
OUT
IN
= 0V
Typ
600
3.8
= 0V
1,000
Max
4.5
Units
ns
V
5