AD1836AASZ Analog Devices Inc, AD1836AASZ Datasheet - Page 6

• Manufacturer Part Number: AD1836AASZ
• Description: IC CODEC 4ADC/6DAC 24 BIT 52MQFP
• Manufacturer: Analog Devices Inc
• Type: General Purposer

Specifications of AD1836AASZ

• Data Interface: Serial
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 4 / 6
• Sigma Delta: Yes
• S/n Ratio, Adcs / Dacs (db) Typ: 105 / 108
• Dynamic Range, Adcs / Dacs (db) Typ: 105 / 108
• Voltage - Supply, Analog: 4.75 V ~ 5.25 V
• Voltage - Supply, Digital: 4.75 V ~ 5.25 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 52-BQFP
• Audio Codec Type: Stereo
• No. Of Adcs: 4
• No. Of Dacs: 6
• No. Of Input Channels: 4
• No. Of Output Channels: 6
• Adc / Dac Resolution: 24bit
• Adcs / Dacs Signal To Noise Ratio: 108dB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD1836AZ-DBRD - BOARD EVAL FOR AD1836AAD1836A-DBRD - BOARD EVAL FOR AD1836A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

AD1836A
Table 7. Timing Specifications
Parameter
MASTER CLOCK AND RESET
SPI PORT
DAC SERIAL PORT
(Normal Modes)
DAC SERIAL PORT
(Packed 128 Mode, Packed 256 Mode)
ADC SERIAL PORT
(Normal Modes)
ADC SERIAL PORT
(Packed 128 Mode, Packed 256 Mode)
ADC SERIAL PORT
(TDM Packed AUX)
AUXILIARY INTERFACE
t
t
t
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
f
t
t
t
t
t
t
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
MCLK
DB
DB
MH
ML
MCLK
PDR
PDRR
CHH
CHL
CDS
CDH
CLS
CLH
CODE
COD
COH
COTS
DBH
DBL
DLS
DLH
DDS
DDH
DBH
DBL
DLS
DLH
DDS
DDH
ABD
ALS
ABDD
ABD
ALS
ABDD
ABD
ALS
ABDD
DDS
DDH
AXDS
AXDH
DXDD
MCLK High
MCLK Low
MCLK Period
MCLK Frequency
PD/RST Low
PD/RST Recovery
CCLK High
CCLK Low
CDATA Setup
CDATA Hold
CLATCH Setup
CLATCH Hold
COUT Enable
COUT Delay
COUT Hold
COUT Three-State
DBCLK High
DBCLK Low
DBCLK Frequency
DLRCLK Setup
DLRCLK Hold
DSDATA Setup
DSDATA Hold
DBCLK High
DBCLK Low
DBCLK Frequency
DLRCLK Setup
DLRCLK Hold
DSDATA Setup
DSDATA Hold
ABCLK Delay
LRCLK Skew
ASDATA Delay
ABCLK Delay
LRCLK Skew
ASDATA Delay
ABCLK Delay
LRCLK Skew
ASDATA Delay
DSDATA1 Hold
DSDATA1 Hold
AAUXDATA Setup
AAUXDATA Hold
DAUXDATA Delay
Rev. 0 | Page 6 of 24
Comments
512 × f
512 × f
512 × f
512 × f
Reset to Active Output
To CCLK Rising
From CCLK Rising
To CCLK Rising
From CCLK Falling
From CCLK Falling
From CCLK Falling
From CCLK Falling
From CCLK Falling
To DBCLK Rising
From DBCLK Rising
To DBCLK Rising
From DBCLK Rising
To DBCLK Rising
From DBCLK Rising
To DBCLK Rising
From DBCLK Rising
From MCLK Transition, 256 × f
From MCLK Rising, 512 × f
From ABCLK Falling
From ABCLK Falling
From MCLK Transition, 256 × f
From MCLK Rising, 512 × f
From ABCLK Falling
From ABCLK Falling
From MCLK Transition, 256 × f
From MCLK Rising, 512 × f
From ABCLK Falling
From ABCLK Falling
To ABCLK Rising
From ABCLK Rising
To AUXBCLK Rising
From AUXBCLK Rising
From AUXBCLK Falling
S
S
S
S
Mode
Mode
Mode
Mode
S
S
S
Mode
Mode
Mode
S
S
S
Mode
Mode
Mode
18
18
36
5
10
10
5
5
5
5
0
15
15
64 × f
0
10
0
20
15
15
256 × f
0
10
0
20
–2
–2
–2
0
7
7
10
Min
4500
S
S
Max
27
10
10
10
15
+2
5
15
+2
5
15
+2
5
25
ns
ns
ns
Unit
ns
ns
ns
MHz
ns
t
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MCLK