XE3005I064TRLF Semtech, XE3005I064TRLF Datasheet

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... Easy interfacing to various DSPs Direct connection to microphone and speaker Various programming options 1.8 – 3 – 48 kHz Package Ext. part no. Temp. range TSSOP 20 pins XE3005I033TRLF -20 to 70° C Lead free XE3005I064TRLF -20 to 70° C uCSP® 20 balls TSSOP 24 pins XE3006I019 -20 to 70° C www.semtech.com ...

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... Register Functional Summary ................................................................................................................................. 28 7.2 Register Definitions ................................................................................................................................................. 29 8 Mechanical Information ........................................................................................................................................ 33 8.1 XE3005 package size (TSSOP20) .......................................................................................................................... 33 8.2 XE3005 package size (5x4 uCSP 8.3 XE3006 Package size (TSSOP24).......................................................................................................................... 35 9 XE3005 Land pattern recommendations (5x4 uCSP © Semtech 2005 Table of Contents ® ) ........................................................................................................................ 34 ® )....................................................................................... 36 2 XE3005/XE3006 www.semtech.com ...

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... DEVICE DESCRIPTION Figure 1: Pin layout of the XE3006 and XE3005 in TSSOP XEMICS TOP VIEW The XE3006 is available in a TSSOP24 package. The XE3005 is available in a TSSOP20 and uCSP® package. Detailed information is found in chapter 8, Mechanical Information. © Semtech 2005 1 1 MCLK MOSI SMAD ...

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... MOSI Note: ( Analog Input DI = Digital Input DI/O = Digital In or Out PU = internal Pull Up ZI impedance In or Out © Semtech 2005 1 Type Master Clock. MCLK derives the internal clocks of ADC and DI DAC DO Sandman output ADC DO Sandman output DAC AI Digital power supply Reset signal generated by the CODEC. If required, the reset ...

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... With the default register settings the ADC can run at a sampling frequency kHz. When used with a sampling frequency higher than 20 kHz, then register C has to be changed. The whole ADC chain can be powered-down through register I. © Semtech 2005 DAC ADC Power Amplifier ...

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... VREG11 provides a 1.1 V reference voltage. The VREG11 can deliver µA. VREG11 is enabled through control register E. VREG16 is a regulated voltage of typically 1.6V and can deliver mA.VREG16 is always enabled. Figure 4: Typical microphone interface (1 bias through VREG11) * depends on microphone type Figure 5: Typical microphone interface (1 bias through VREG16) © Semtech 2005 Vcc 4 0.1µ ...

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... VDDPA VSSPA -VDDPA 1/(256 x Fsync) The DAC receives 16-bit wide 2’s complement format through the Serial Audio Interface. The protocol can be selected through register J. The complete DAC and PA amplifier chain can be powered-down through register I. © Semtech 2005 P Pulse Width Modulator N pwm_in(5:0) ...

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... In master mode the CODEC generates the BLCK and FSYNC signals. In that case the BLCK operates at 32 times the frequency of FSYNC. The CODEC master mode can be used with the LFS protocol only. The register J is used for the different setups of the serial audio interface. © Semtech 2005 Div_factor BCLK ...

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... When the signal falls below the Reference (time = 9) and remains below the Reference until the off-time counter has reached the off-time, the SMAD signal is changed into the inactive (low) state (time = 10). © Semtech 2005 Serial Audio Interface Σ ...

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... The Sandman™ function is illustrated in Figure 9 and is valid for both SMAD (related to the ADC signal) and SMDA (related to the DAC signal). AIN/SDO (AOUT/SDI) On-time counter Off-time counter SMAD (SMDA © Semtech 2005 Reg I, bit 4 Sandman Interface Serial Audio PWM Interface DAC on-time ...

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... NRESET is in the high state (VDD). MCLK NRESET Figure 11: Startup sequence and NRESET signal after power-on. The user can use the NRESET pin in 3 different ways and combinations: © Semtech 2005 XE3005/XE3006 21 VDD = 1.8..3.3V VREG16 = 1.6V VREF = 1.2V ...

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... MCLK, BCLK and FSYNC, the power consumption will reach the standby current of typically 16µA. Use the standard procedure for power up (see start-up and initialization procedure) after a hardware power down and apply your registers setup procedure. © Semtech 2005 delay delay ...

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... SDI SDO 15 14 msb Figure 13: Audio interface timing LFS mode, channel 1 channel 1, sample n FSYNC BCLK n n SDI SDO 15 14 msb Figure 14: Audio interface timing in SFS mode, channel 1 © Semtech 2005 XE3005/XE3006 channel 2, no data lsb channel 2, sample lsb 13 channel 1, sample n+1 - ...

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... Logic values at SPI pins during power-up There are 3 bits inside the registers which are configured depending on the logic values of the pins SS, SCK and MOSI during the power up startup sequence as described in section 2.1.10 Value at power SCK = 0 SCK = 1 MOSI = 0 MOSI = 1 © Semtech 2005 channel 1, no data channel 2, sample ...

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... Transmission in either direction bytes with MSB first. The SS pin should be kept low during the whole transfer of data. There are three timing constraints: Recovery time (t ) between the falling edge of SS and the falling edge of SCK. - recovery © Semtech 2005 1/F sck … … Figure 16: SPI signal timing 15 ...

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... A(4:0)>) miso 3.3.2.2 Write Mode Write communication always takes place in pairs of bytes. The format of the 2 bytes is: Bit 7 mosi 1 Bit 7 mosi msb © Semtech 2005 Max Unit Comments - clock period of the master clock MCLK master 0 frequency of the master clock MCLK ...

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... Off-time (15:0): Time until power down. The number of sequential samples that have to be lower than the Reference for the power down signal to become active. The Sandman™ function is disabled (SMAD or SMDA at logic 1) if this parameter is zero. The ADC and DAC have one common Off-time value. © Semtech 2005 msb A4 ...

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... Off-time at least 10ms, the Off-time should be longer than 1/f frequency = 100Hz if FSYNC = 20kHz. The value of f high-pass filter in the ADC filters out signals below 100Hz. • Reference should be adjusted just above the noise level. © Semtech 2005 Off-time(15:0) Sandman (SMAD or SMDA) don’t care logic 1 (disable function) don’ ...

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... Supply voltage, VDD Analog signal peak input voltage, AIN (gain = 20x) Analog signal peak input voltage, AIN (gain = 5x) Differential output load resistance Master clock frequency ADC or DAC conversion rate Operating free-air temperature, TA © Semtech 2005 XE3005/XE3006 Conditions Min Max -0.3 3.65 ...

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... PSRR Power supply rejection ratio, input referred Cin Input capacitor Rin Input resistance VIN – VSSA Eg gain error offset error input noise INL Integral non linearity DNL Differential non linearity © Semtech 2005 XE3005/XE3006 Test Min Typ Conditions IO = -360uA 2 2mA VSSD-0.5 VIH = 3.3 V VIL = 0.6 V ...

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... Supply current in standby mode Stand-by mode @ VDD = 1.8V 25°C Parameter Istb1 Supply current in standby mode Istb2 Supply current in standby mode Istb3 Supply current in standby mode © Semtech 2005 Test Conditions Min Bandwidth 10 kHz 72 1⁄4 full scale Bandwidth 10 kHz 72 FSYNC = 20 kHz ...

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... Normal operations @ VDD = 1.8V, FSYNC = 48 kHz 25°C, Register C(7:0) = 0xC4 Parameter IDD Supply current CODEC IADC Supply current ADC IDAC Supply current DAC © Semtech 2005 Test Conditions Min ADC on, DAC on FSYNC = 20 kHz, no load ADC on, DAC off FSYNC = 20 kHz, no load ADC off, DAC on ...

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... Hold time data input SDI after BCLK low 11 Delay time SDO valid after BCLK high 12 Setup time data input FSYNC to BCLK low 13 Hold time data input FSYNC after BCLK low *see figure 18,19 for LFS and 20, 21 for SFS © Semtech 2005 Test Min Conditions 1024 45 T/4 T/4 ...

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... Timing diagram of the serial audio interface – LFS mode MCLK 5 BCLK 4 FSYNC SDI MCLK 8 BCLK 9 FSYNC 10 SDI D15 D14 D13 D12 D11 SDO D15 D14 D13 D12 D11 © Semtech 2005 Figure 18: LFS, timing diagram 11 D10 D10 Figure 19: LFS, zoom timing diagram 24 XE3005/XE3006 ...

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... Timing diagram of the serial audio interface – SFS mode MCLK 4 BCLK FSYNC SDI MCLK 8 BCLK FSYNC D15 D14 D13 D12 D11 SDI SDO D15 D14 D13 D12 © Semtech 2005 Figure 20: SFS, timing diagram 11 D10 D11 D10 Figure 21: SFS zoom timing diagram 25 XE3005/XE3006 ...

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... Recovery Time 3 Disable Time 4 Setup time MISO valid to SCK high 5 Hold time MISO valid after SCK high 6 Delay time MOSI valid after SCK low * see figure SCK MISO MOSI © Semtech 2005 Test Conditions SCK C = 10pF Load Figure 22: Serial Peripheral Interface timing 26 ...

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... Capacitor for Vref: 1 µF • Resistor for Vref: 390 kΩ • Capacitor for VREG16: 1 µF The low pass filter between the DAC output and the speaker depends on the CODEC settings and the speaker type. © Semtech 2005 1 MCLK MOSI 24 Vcc SS ...

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... Register J Register L Register M Register N Register O Register P © Semtech 2005 Description ADC current setting. The data in this register has the following functions: • Adjust the ADC current for FSYNC > 20kHz • 0xF0 for FSYNC<= 20 kHz, 0xC4 for FSYNC > 20 kHz. Analog Input. The data in this register has the following functions: • ...

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... J 0x09 K 0x0A L 0x0B M 0x0C N 0x0D O 0x0E P 0x0F © Semtech 2005 Name Reserved Reserved ADC current Reserved Analog input Reserved Reserved Reserved Block on/off and clock division Audio interface configuration Reserved Sandman™ function, off-time byte 1 Sandman™ function, off-time byte 2 Sandman™ ...

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... Register I (7:0) block on/off and address 0x08 clock division 7:4 3 EN_DAC 2 EN_ADC 1:0 MCLKDIV © Semtech 2005 Default value: Description 0xF0 0xF0 0xF0 for FSYNC<= 20 kHz, 0xC4 for FSYNC > 20 kHz. Default value 0x08/0x0C 0 Generation of the microphone supply at pin VREG11: 1: enables VREG11 ...

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... Sandman™ function, address 0x0C most significant byte 7:0 SM_OFF_MSB Register N (7:0) Sandman™ function, address 0x0D 7:0 © Semtech 2005 Default Description value 0x25/ 0x24 0 0: disable loopback, normal mode 1: enable loopback => The CODEC connects internally the ADC output to DAC input ...

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... Register O (7:0) Sandman™ function, address 0x0E reference for ADC 7:0 Register P (7:0) Sandman™ function, address 0x0F reference for DAC 7:0 © Semtech 2005 Default value 0x00 SMAD_REF 00000000 Default value 0x00 SMDA _REF 00000000 32 XE3005/XE3006 Description Reference amplitude for ADC for Sandman™ ...

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... Z 20 pin 1 index 1 e DIMENSIONS (mm are the original dim ensions) A UNIT max. 0.15 0.95 0.30 mm 1.10 0.25 0.05 0.80 0.19 Plastic Thin Shrink Small Outline Package, 20 leads, body width: 4.4 mm © Semtech 2005 0.2 6.6 4.5 6.6 0.75 0.65 1.0 0.1 6 ...

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... XE3005 PACKAGE SIZE (5X4 UCSP SIDE VIEW XEMICS TOP VIEW P Nominal dimensions in mm sion < 0.8 0.31 0.46 © Semtech 2005 ® ) PACKAGE OUTLINE of the XE3005 uCSP 2.745 3.225 0.37 1.95 max ± 0.075 ± 0.125 Figure 25: 5x4 uCSP Ultra Chip Scale Package balls array. ...

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... Z 24 pin 1 index DIMENSIONS (mm are the origina l dimensions) A UNIT max. 0.15 0.95 0.30 mm 1.10 0.25 0.05 0.80 0.19 Plastic Thin Shrink Small Outline Package with 24 leads and a body width of 4.4 mm. © Semtech 2005 0.2 7.9 4.5 6.6 0.75 0.65 1.0 0.1 7 ...

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... XE3005 LAND PATTERN RECOMMENDATIONS (5X4 UCSP Nominal dimensions in mm sion 3.35 0.65 2.82 Figure 27: Land pattern recommendations (5x4 uCSP®) © Semtech 2005 PAD Ø 0.25 PASTE_MASK Ø 0.25 SOLDER_MASK Ø 0.35 PLACEMENT OUTLINE 0.60 0.325 0 36 XE3005/XE3006 ® ) LAND PATT LAND PATTERN RECOMMENDATION ® ...

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... No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. Semtech. assumes no responsibility or liability whatsoever for any failure or unexpected operation resulting from misuse, neglect improper installation, repair or improper handling or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified range ...