XE3005I064TRLF Semtech, XE3005I064TRLF Datasheet - Page 16

IC CODEC LOW PWR 16BIT 20-UCSP

XE3005I064TRLF

Manufacturer Part Number
XE3005I064TRLF
Description
IC CODEC LOW PWR 16BIT 20-UCSP
Manufacturer
Semtech
Type
Audio Codecr
Datasheet

Specifications of XE3005I064TRLF

Data Interface
Serial
Resolution (bits)
16 b
Number Of Adcs / Dacs
1 / 1
Sigma Delta
Yes
S/n Ratio, Adcs / Dacs (db) Typ
78 / 78
Dynamic Range, Adcs / Dacs (db) Typ
78 / 78
Voltage - Supply, Analog
1.8 V ~ 3.6 V
Voltage - Supply, Digital
1.8 V ~ 3.6 V
Operating Temperature
-20°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
20-UCSP®
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
XE3005I064TR
3.3.2
There are two SPI modes: read and write.
3.3.2.1
Read communication always takes place in pairs of bytes. A read request of 2 bytes is sent on the MOSI line. The
content of the addressed register, one byte, is dumped on the MISO line during the transmission of the second byte on
the MOSI. The formats of one byte are the following:
3.3.2.2
Write communication always takes place in pairs of bytes. The format of the 2 bytes is:
© Semtech 2005
-
-
SPI Interface Modes
Read Mode
Write Mode
sck
mosi
miso
Delay
t
t
F
Disable time (t
SCK frequency (F
mosi
miso
mosi
mosi
recover
disable
Bit
Bit
bit
bit
ss
SCK
2 x T
1
msb
msb
Min
125
1
7
1
7
7
7
disable
master
1
SCK
request (read <address A(4:0)>)
) between the last rising edge of SCK and the rising edge of SS.
)
0
0.5 x F
6
1
6
6
0
6
A4
Max
Figure 17: SPI signal timing in read mode
-
-
master
A3
5
0
5
5
0
5
A2
Unit
Hz
ns
ns
A1
msb
16
A0
4
msb
4
4
4
Comments
D(7:0)
D(7:0)
T
F
master
msb
1
master
= clock period of the master clock MCLK
= frequency of the master clock MCLK
1
3
3
3
3
read data D(7:0) of address A(4:0)
0
A (4:0)
A(4:0)
2
2
2
2
XE3005/XE3006
1
1
1
1
lsb
lsb
lsb
lsb
lsb
0
0
0
0
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