MAX9867EWV+T Maxim Integrated Products, MAX9867EWV+T Datasheet - Page 24

• Manufacturer Part Number: MAX9867EWV+T
• Description: IC STEREO AUD CODEC LP 30WLP
• Manufacturer: Maxim Integrated Products
• Type: Stereo Audior

Specifications of MAX9867EWV+T

• Data Interface: I²C, Serial
• Resolution (bits): 18 b
• Number Of Adcs / Dacs: 2 / 2
• Sigma Delta: Yes
• Dynamic Range, Adcs / Dacs (db) Typ: 85 / 90
• Voltage - Supply, Analog: 1.65 V ~ 1.95 V
• Voltage - Supply, Digital: 1.65 V ~ 1.95 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 30-WLP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: MAX9867EWV+T; MAX9867EWV+TTR

Ultra-Low Power Stereo Audio Codec
Hardware interrupts are reported on the open-drain IRQ
pin. When an interrupt occurs, IRQ remains low until the
interrupt is serviced by reading the status register 0x00.
If a flag is set, it is reported as a hardware interrupt only
if the corresponding interrupt enable is set. Each bit
enables interrupts for the status flag in the respective
bit location in register 0x00. See Table 3.
SDODLY is used to control the SDOUT timing. See the
Digital Audio Interface section for a detailed description.
The MAX9867 can work with a master clock (MCLK)
supplied from any system clock within the 10MHz-to-
60MHz range. Internally, the MAX9867 requires a
10MHz-to-20MHz clock. A prescaler divides MCLK by
1, 2, or 4 to create the internal clock (PCLK). PCLK is
used to clock all portions of the MAX9867. See Table 4.
The MAX9867 is capable of supporting any sample rate
from 8kHz to 48kHz, including all common sample rates
(8kHz, 16kHz, 24kHz, 32kHz, 44.1kHz, and 48kHz). To
Table 3. Interrupt Register
Table 4. Clock Control Registers
24
Interrupt Enable
System Clock
Stereo Audio Clock
Control High
Stereo Audio Clock
Control Low
______________________________________________________________________________________
PSCLK
BITS
REGISTER
REGISTER
MCLK Prescaler
Divides MCLK to generate a PCLK between 10MHz and 20MHz.
00 = Disable clock for low-power shutdown.
01 = Select if MCLK is between 10MHz and 20MHz.
10 = Select if MCLK is between 20MHz and 40MHz.
11 = Select if MCLK is between 40MHz and 60MHz.
ICLD
PLL
B7
B7
0
Hardware Interrupts
ISLD
B6
B6
0
Clock Control
IULK
B5
B5
PSCLK
NI[7:1]
B4
B4
0
accommodate a wide range of system architectures,
the MAX9867 supports three main clocking modes:
• Normal: This mode uses a 15-bit clock divider coeffi-
• Exact Integer: In both master and slave mode, com-
• PLL: When operating in slave mode, a PLL can be
FUNCTION
cient to set the sample rate relative to the prescaled
MCLK input (PCLK). This allows high flexibility in both
the MCLK and LRCLK frequencies and can be used
in either master or slave mode.
mon MCLK frequencies (12MHz, 13MHz, 16MHz,
and 19.2MHz) can be programmed to operate in
exact integer mode for both 8kHz and 16kHz sample
rates. In these modes, the MCLK and LRCLK rates
are selected by using the FREQ bits instead of the NI
and PLL control bits.
enabled to lock onto externally generated LRCLK
signals that are not integer related to PCLK. Prior to
enabling the interface, program NI to the nearest
desired ratio and set the NI[0] = 1 to enable the
PLL’s rapid lock mode. If NI[0] = 0, then NI is ignored
and PLL lock time is slower.
NI[14:8]
B3
B3
0
SDODLY
B2
B2
FREQ
IJDET
B1
B1
NI[0]
B0
B0
0
REGISTER
REGISTER
ADDRESS
0x04
0x05
0x06
0x07