CS42324-CQZ Cirrus Logic Inc, CS42324-CQZ Datasheet
CS42324-CQZ
Specifications of CS42324-CQZ
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CS42324-CQZ Summary of contents
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... Oversampling Filter Stereo ADC This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice. Copyright © Cirrus Logic, Inc. 2008 (All Rights Reserved) CS42324 0.5 dB Step Size Left-Justified I²S Features, General Description, and Order- page 2 ...
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... Integrated digital level translators allow easy interfacing between the CS42324 and other devices operating over a wide range of logic levels. The CS42324 is available in a 48-pin LQFP package in Commercial (-40°C to +85°C) and Automotive (-40°C to +105°C) grades. The CDB42324 Customer Demonstra- tion board is also available for device evaluation and implementation suggestions. Please refer to information” ...
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... Internal Digital Loopback ....................................................................................................... 35 4.4.5 DAC Description .................................................................................................................... 35 4.4.6 Analog Output Multiplexer ..................................................................................................... 36 4.4.7 Output Transient Control ....................................................................................................... 36 4.4.8 Mute Control .......................................................................................................................... 37 4.5 Initialization ..................................................................................................................................... 37 4.5.1 Determining Hardware or Software Mode ............................................................................. 37 4.5.2 Hardware Mode Start-Up ...................................................................................................... 37 4.5.3 Software Mode Start-Up ........................................................................................................ 38 4.5.4 Initialization Flow Chart ......................................................................................................... 39 4.6 Device Control ................................................................................................................................ 40 DS721A6 CS42324 3 ...
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... DAC2 Digital Interface Format (DAC2_DIF) .......................................................................... 52 6.9 ADC Control (Address 0Ah) ........................................................................................................... 52 6.9.1 ADC High-Pass Filter Freeze ................................................................................................ 52 6.9.2 ADC Soft Ramp Control ........................................................................................................ 52 6.9.3 Analog Input Selection .......................................................................................................... 53 6.10 DAC1 Control (Address 0Bh) ....................................................................................................... 53 6.10.1 DAC1 De-Emphasis Control ................................................................................................ 53 6.10.2 DAC1 Single Volume Control .............................................................................................. 53 4 CS42324 DS721A6 ...
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... ADC Positive Overflow Interrupt Bit (ADC_OVFLP) ............................................................ 62 6.20.8 ADC Negative Overflow Interrupt Bit (ADC_OVFLN) .......................................................... 63 7. GROUNDING AND POWER SUPPLY DECOUPLING ........................................................................ 64 8. ADC FILTER PLOTS ........................................................................................................................... 65 9. DAC DIGITAL FILTER RESPONSE PLOTS 10. PARAMETER DEFINITIONS .............................................................................................................. 69 11. PACKAGE DIMENSIONS ................................................................................................................. 70 THERMAL CHARACTERISTICS AND SPECIFICATIONS ................................................................. 70 12. ORDERING INFORMATION .............................................................................................................. 71 13. REVISION HISTORY .......................................................................................................................... 71 DS721A6 ................................................................................ 67 CS42324 5 ...
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... Table 1. I/O Power Rails ........................................................................................................................... 12 Table 2. Speed Modes .............................................................................................................................. 28 Table 3. Single-Speed Mode Common Clock Frequencies ...................................................................... 28 Table 4. Double-Speed Mode Common Clock Frequencies ..................................................................... 28 Table 5. M1 and M0 Mode Pins in Hardware Mode .................................................................................. 29 Table 6. Slave Mode SCLK/LRCK Ratios ................................................................................................. 30 Table 7. MCLKx to LRCKx Ratios ............................................................................................................. 30 Table 8. Hardware Mode Interface Format Control ................................................................................... 32 6 CS42324 DS721A6 ...
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... Table 9. Hardware Mode Feature Summary ............................................................................................. 40 Table 10. Freeze-able Bits ........................................................................................................................ 48 DS721A6 CS42324 7 ...
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... This pin will become a high-impedance out- put during power-down mode or when an invalid MCLK to LRCK ratio is detected CS42324 Pin Description CS42324 OVFL RST 35 AIN1A 34 33 AIN1B AIN2A 32 31 AIN2B 30 AIN3A 29 AIN3B AIN4A 28 27 AIN4B 26 AIN5A 25 AIN5B DS721A6 ...
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... Master Clock 1 (Input) - Clock source for the ADC’s delta-sigma modulators. By default, this sig- MCLK1 48 nal also clocks the DAC’s delta-sigma modulators. DS721A6 “I/O Power Rails” on page 12. Refer to for appropriate voltages. CS42324 the“Recommended Operating 9 ...
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... This pin will become a high-impedance out- put during power-down mode or when an invalid MCLK to LRCK ratio is detected CS42324 Pin Description CS42324 OVFL RST 35 AIN1A 34 AIN1B 33 AIN2A 32 31 AIN2B 30 AIN3A 29 AIN3B AIN4A 28 27 AIN4B 26 AIN5A 25 AIN5B DS721A6 ...
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... Master Clock 1 (Input) - Clock source for the ADC’s delta-sigma modulators. By default, this sig- MCLK1 48 nal also clocks the DAC’s delta-sigma modulators. DS721A6 “I/O Power Rails” on page 12. Refer to for appropriate voltages CS42324 the“Recommended Operating 11 ...
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... Input - Output 1 3.3 V, CMOS Output 1 3.3 V, Open Drain Output 9 12.0 V Table 1. I/O Power Rails CS42324 Receiver 1 3.3 V, with Hysteresis 1 3.3 V, with Hysteresis 1 3.3 V, with Hysteresis 1 3.3 V, with Hysteresis 1 3.3 V, with Hysteresis 1 3.3 V, with Hysteresis 1 3.3 V, with Hysteresis 1 3.3 V, with Hysteresis 1 3.3 V, with Hysteresis 1 ...
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... Commercial(-CQZ) T -40 A Automotive(-DQZ) -40 (Note 1) Symbol Analog VA Digital VD Logic VL High Voltage Analog VA_H (Note INA Logic V IND stg CS42324 Nom Max Units 3.3 3.47 V 3.3 3.47 V 3.3 3.47 V 9.0 12.60 V °C - +85 °C - +105 Min Max Units -0.3 +4.50 V -0.3 +4 ...
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... A-weighted unweighted (Note -20 dB -60 dB THD - kHz) I OUT (Note (Note OUT 16. R and C reflect the minimum resistance and maximum capacitance L L beyond 100 pF can cause the internal op-amp to become unstable. L CS42324 = 25° Min Typ Max 94 100 - -90 -84 - -77 -73 - -37 -33 - -87 ...
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... C to +85° C; 997 Hz Full-Scale Output Sine Wave. A Symbol Min (Note 3) A-weighted 90 unweighted 87 A-weighted 83 unweighted 80 (Note - -60 dB THD - - kHz 1 OUT (Note (Note OUT CS42324 Figure 7 on page 26 and Fig- Typ Max Unit 100 - -90 -80 dB -77 -67 dB -37 -27 dB -87 -77 dB -77 -67 dB -37 -27 dB -100 - dB 0.1 0.25 dB 100 - ppm/°C 2 ...
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... AOUTx R GND Figure 1. Equivalent Analog Output Load 16 Symbol to -0.01 dB corner corner (Note 6) tgd Fs = 44.1 kHz to -0.01 dB corner corner (Note 6) tgd 125 100 V out 2.5 Figure 2. Maximum Analog Output Loading CS42324 Min Typ Max 0 - .454 0 - .499 -0.01 - +0.01 0.547 - - 102 - - - 9.4/ +/-0. .43 ...
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... Interchannel Isolation Note: 8. Referred to the typical line-level full-scale input voltage. DS721A6 27 kHz or 96 kHz; Synchronous Mode; Measurement Bandwidth Symbol Min A-weighted 89 unweighted 86 (Note THD A-weighted 89 unweighted 86 (Note THD 0.576• kHz) - CS42324 = 25° Figure Typ Max Unit -88 - -88 - 0.1 - ...
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... Referred to the typical line-level full-scale input voltage -40° +85° C; 997 Hz Input Sine Wave. Decoupling A Figure 7 on page 26 Symbol Min A-weighted 85 unweighted 82 (Note THD A-weighted 85 unweighted 82 (Note THD 0.576• kHz) - CS42324 and Figure 8 on page Typ Max Unit -88 - -88 - ...
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... Notes: 10. Response is clock dependent and will scale with sample rate (Fs). Note that the response plots (Figures 23 to 30) are normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs. 11. Response shown is for kHz. DS721A6 (Note 10) (Note 11) (Note 11) CS42324 Symbol Min Typ Max 0 - 0.489 ...
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... AC-Load Resistance Load Capacitance Output Impedance Interchannel Isolation Note: 12. Referred to the typical line-level full-scale input voltage. 20 Symbol Min A-weighted 89 unweighted 86 (Note THD OUT (Note (Note OUT (1 kHz) - CS42324 = 25° Typ Max Unit -87 - ±0 2 rms 2 rms μA 575 - - - kΩ - 100 pF Ω ...
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... VL=VD=VA=3.3 V VA_H = VL=VD= All supplies - (Note 14) PSRR VCMADC VCMDAC (Note 15 FILT+ VBIAS and Figure 8 on page 27. Symbol Digital Interface V OH MUTEC1/MUTEC2/MUTEC3 V OH Digital Interface V OL MUTEC1/MUTEC2/MUTEC3 CS42324 Min Typ Max - 200 - - 216 289 - 169 225 - 0 0.5• VA-0.8 - Min ...
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... SETUP1 after SCLK rising t HOLD1 before SCLK rising t SETUP2 after SCLK rising t HOLD2 28. Section 4.2.1 Master Mode on page 30 30. t PERIOD t SETUP1 channel t SETUP2 data Figure 3. Serial Input Timing CS42324 Min Typ Max Unit 1.024 - 41.4720 MHz kHz 50 108 64•Fs - 64•Fs 72.3 ...
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... SCLKx t HOLD1 LRCKx channel SDINx data DS721A6 = 20 pF. L Symbol before SCLK rising t SETUP3 after SCLK rising t HOLD3 before SCLK rising t SETUP3 after SCLK rising t HOLD3 t PERIOD t SETUP1 channel t SETUP3 data Figure 4. Serial Output Timing CS42324 Min Typ Max Unit HIGH t HOLD3 23 ...
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... Symbol f scl t irs t buf t hdst t low t high t sust (Note Note:) t hdd t sud susp t ack Repeated Start t high t t sud t sust hdd CS42324 Min Max Unit - 100 kHz 500 - ns 4.7 - µs 4.0 - µs 4.7 - µs 4.0 - µs 4.7 - µ µs 250 - µs - ...
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... CDIN CDOUT DS721A6 = 20 pF. L Symbol f sclk t srs t spi t csh t css t scl t sch t dsu (Note 23 css t scl t sch dsu scdov t scdov Figure 6. Software Mode Timing - SPI Mode CS42324 Min Max Unit - 6 MHz 500 - ns 500 - ns 1.0 - µ 100 ns - 100 ns - 100 ns - 100 all other times. ...
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... SDOUT AIN2B INT OVFL AIN3A RST SCL/CCLK AIN3B SDA/CDOUT AD0/CS AIN4A AD1/CDIN AIN4B AIN5A VL 0.1 µF AIN5B GND GNDH CS42324 + + µF Optional Analog Muting 470 Ω 2 Vrms Left Analog Out kΩ 3.3 µF * See Note 2 * 3.3 µF 10 kΩ Vrms Right 470 Ω ...
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... Fs R 470 ext This circuitry is intended for applications where the CS42324 connects directly to a line level output. For internal routing applications please see the DAC Analog Output Characteristics section for loading limitations the load ext impedance See SOC/DSP Note 2 +1 ...
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... APPLICATIONS 4.1 System Clocking The CS42324 will operate at sampling frequencies from 4 kHz to 108 kHz. This range is divided into two speed modes as shown in Speed Mode Single-Speed Double-Speed The CS42324 has two serial ports which can operate synchronously or asynchronously. Serial Port 1 (SP1) consists of the SCLK1 and LRCK1 signals. Serial Port 2 (SP2) consists of the SCLK2 and LRCK2 signals ...
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... SP2_SPEED bits, and MCLK2 does not need to be provided (the MCLK2 pin should be left unconnected if not required). If the SPx_MCLK (SPx = SP1 and/or SP2) bits in serial ports 1 and 2 are set differently, the CS42324 will operate in Asynchronous Mode. The serial ports will operate asynchronously with Serial Port 1 clocked from its SP1_MCLK selection and Serial Port 2 clocked from its SP2_MCLK selection ...
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... Single Speed Mode 32, 48, 64, 128 Table 6. Slave Mode SCLK/LRCK Ratios MCLKx to LRCKx Ratio Single Speed Mode 256, 384, 512, 768 256, 512 Table 3 an Table 4 on page 28 for clock ratio configuration. Table 7. MCLKx to LRCKx Ratios CS42324 Figure 10. ÷256 0 Generated-LRCK1 ÷128 1 SP1_SPEED ÷4 0 Generated-SCLK1 ÷ ...
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... DAC1_SP 0 Internal-LRCK1 1 Internal-LRCK2 DAC1 0 Internal-SCLK1 1 Internal-SCLK2 DAC1_DIF[2:0] SDIN1 Figure 11. Converter Clocking Transm itting Device #2 3ST_SDOUT SDOUT 3ST_SPx SCLKx/LRCKx Receiving Device Figure 12. Tri-State Serial Port CS42324 Figure 9 on page 29); the internal DAC2_MCLK 0 Internal-MCLK1 1 Internal-MCLK2 DAC2_SP 0 Internal-LRCK1 1 Internal-LRCK2 DAC2 0 Internal-SCLK1 1 Internal-SCLK2 DAC2_DIF[2:0] SDIN2 ...
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... To ensure synchronous sampling, the master clocks and left/right clocks must be the same for all of the CS42324’s in the system. If only one master clock source is needed, one solution is to place one CS42324 in Master Mode, and slave all of the other devices to the one master. ...
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... Analog-to-Digital Data Path 4.3.1 ADC Analog Input Multiplexer AINxA and AINxB are the analog inputs, internally biased to VCMADC. The CS42324 contains a stereo 5-to-1 analog input multiplexer which can select one of 5 possible stereo analog input sources and route it to the ADC. ...
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... When using operational amplifiers in the input circuitry driving the CS42324, a small DC offset may be driven into the A/D converter. The CS42324 includes a high-pass filter after the decimator to remove any DC offset which could result in recording a DC level, possibly yielding clicks when switching between de- vices in a multichannel system ...
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... Internal Digital Loopback The CS42324 supports an internal digital loopback mode in which the ADC’s output data can be internally routed to either of the DAC inputs. This mode may be activated by setting the DACx_LOOP_BACK bit in “DAC1 Control (Address 0Bh)” on page 53 mode, the ADC and DAC will need to operate at the same synchronous sample rate. When the DACx_LOOP_BACK bit is set, the respective DACx_DIF[2:0] bits must be set to the same value as the ADC_DIF[2:0] register ...
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... Output Transient Control The CS42324 uses Popguard technology to minimize the effects of output transients during power-up and power-down. This technique eliminates the audio transients commonly produced by single-ended single- supply converters when it is implemented with external DC-blocking capacitors connected in series with the audio outputs ...
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... It is recommended that RST be activated if the analog or digital supplies drop below the recommended operating condition to prevent power-glitch-related issues. DS721A6 Figure 19 on page 39. The modes of configuration for this mode can be 40. Because of the limited configuration abilities in Hard- CS42324 Figure 19 on page 39. The CODEC en- 37 ...
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... Using the appropriate registers, 9Mute the AOUTxA, AOUTxB, DAC’s & ADC’s. 2. Set the PDN bit in the power control register to ‘1’b. The CODEC will not power down until it reaches a fully muted sate. 3. Bring RST low. 38 CS42324 “Software Mode - I²C Control Port” on “Operational Control (Address 02h)” Section 4.1.1. ...
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... RST = Low Pull-up on SDOUT? Software Mode Registers setup to desired settings. RST = Low ERROR: MCLKx/LRCKx ratio change Figure 19. Initialization Flow Chart CS42324 Standby Mode 1. No audio signal generated. Yes 2. Control Port Registers retain PDN bit = '1'b? settings. 3. Update Control Port Registers as Required. No ...
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... In Hardware Mode, a limited feature set may be controlled via hardware control pins. 4.6.1 Hardware Mode A limited feature-set is available when the CS42324 powers up in Hardware Mode (see Power-Up Sequence, Hardware Mode” on page Table 9 shows a list of functions/features, the default configuration and the associated hardware control available ...
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... MAP will be output. Setting the auto increment bit in MAP allows successive reads or writes of consecutive registers. Each byte is separated by an acknowledge bit. The ACK bit is output from the CS42324 after each input byte is read, and is input to the CS42324 from the microcontroller after each transmitted byte. ...
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... If the INCR bit (see Section to read from multiple consecutive registers. Bring CS high when reading is complete. 42 4.6.4.1) is set to 1, repeat the previous step until all the desired registers 25. 4.6.4.1) is set to 1, keep CS low and continue providing clocks on CCLK CS42324 Figure 22 25. “Switching DS721A6 ...
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... Reading the Interrupt Status register will clear the interrupt condtion. The CS42324 also has a dedicated overflow output. The OVFL pin functions as active low open drain and has no active pull-up transistor, thereby requiring an external pull-up resistor. The OVFL pin outputs the ADC Overflow Positive and Negative conditions available in the Interrupt Status register ...
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... DAC1_ DAC1_SOFT DAC1_ZC SNGVOL LOOPBACK DAC2_ DAC2_ DAC2_ SNGVOL SOFT ZC LOOPBACK Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved CS42324 REV3 REV2 REV1 DAC1_ DAC1_ ADC_ MuteL MuteR MuteL Reserved TRI-SDOUT TRI-SP1 MCLK1 MCLK1 Reserved SP1_MCLK FREQ1 FREQ0 MCLK2 MCLK2 ...
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... VOL5 VOL4 SP2_ SP1_ SP1_ CLKERR0 CLKERR1 CLKERR0 DAC2_ DAC1_ DAC1_ AMUTERM AMUTELM AMUTERM DAC2_ DAC1_ DAC1_ AMUTER AMUTEL AMUTER CS42324 ADCA_ ADCA_ ADCA_ VOL3 VOL2 VOL1 ADCB_ ADCB_ ADCB_ VOL3 VOL2 VOL1 DAC1A_ DAC1A_ DAC1A_ VOL3 VOL2 VOL1 DAC1B_ DAC1B_ ...
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... When writing to registers containing “Reserved” bits, all bits marked as “Reserved” must maintain their default values. 6.1 Device I.D. and Revision Register (Address 00h) (Read Only DEVICE3 DEVICE2 DEVICE1 6.1.1 Device I.D. (Read Only) I.D. code for the CS42324. DEVICE[3:0] 0110 CS42324 6.1.2 Chip Revision (Read Only) CS42324 revision level. REV[3:0] 000 A1 001 B0 6 ...
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... When set, this bit places the device in power-down mode. PDN 0 Device is running 1 Device is in power-down mode DS721A6 Mute status of DAC2 Right-channel Mute status of DAC1 Left-channel Mute Status of DAC1 Right-Channel Mute Status of ADC Left-Channel Mute Status of ADC Right-Channel FREEZE Reserved Device Power-Down State CS42324 TRI-SDOUT TRI-SP1 TRI-SP2 47 ...
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... Serial Port 1 is configured as a master 48 INT Pin Polarity FREEZE Status Name Register 01h 0Fh 10h 11h 12h 13h 14h Table 10. Freeze-able Bits SDOUT state SCLK1 and LRCK1 State CS42324 Bit(s) 7:0 7:0 7:0 7:0 7:0 7:0 7:0 DS721A6 ...
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... This bit selects which MCLK pin provides the clock for deriving Master Mode sub-clocks for Serial Port 1. SP1_MCLK 0 MCLK1 1 MCLK2 DS721A6 SCLK2 and LRCK2 State MCLK1 SP1_SPEED FREQ1 Serial Port 1 Master/Slave Select Serial Port 1 Speed Mode MCLK Divider Serial Port 1 MCLK source CS42324 MCLK1 Reserved SP1_MCLK FREQ0 49 ...
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... This bit selects which MCLK pin provides the clock for the ADC. ADC_MCLK 0 MCLK1 1 MCLK2 MCLK2 SP2_SPEED FREQ1 Serial Port 2 Master/Slave Select Serial Port 2 Speed Mode MCLK Divider Serial Port 2 MCLK source ADC_SP Reserved ADC MCLK source CS42324 MCLK2 Reserved SP2_MCLK FREQ0 Reserved ADC_DIF1 ADC_DIF0 DS721A6 ...
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... Left-Justified 24-bit data 01 I² 24-bit data 10 Right Justified, 16-bit data 11 Right Justified, 24-bit data DS721A6 ADC sub clock source ADC Serial Audio Interface Format DAC1_SP Reserved DAC1 MCLK source DAC1 sub clock source DAC1 Serial Audio Interface Format CS42324 Reserved DAC1_DIF1 DAC1_DIF0 51 ...
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... DAC2_SP Reserved DAC2 MCLK source DAC2 sub clock source DAC2 Serial Audio Interface Format Reserved Reserved ADC High-Pass Filter Freeze CS42324 Reserved DAC2_DIF1 DAC2_DIF0 AIN_SEL2 AIN_SEL1 AIN_SEL0 DS721A6 ...
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... DAC1_SOFT 0 Off 1 On DS721A6 ADC Soft Ramp Control ADC Soft Ramp Control DAC1_ DAC1_ZC LOOPBACK μ s/50 DAC1 De-Emphasis Control DAC1 Single Volume Control DAC1 Soft Ramp Control CS42324 2 1 DAC1_INV DAC1_MIX1 DAC1_MIX0 μ s digital de-emphasis filter response for ...
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... These bits implement mono mixes of the left and right channels as well as a left/right channel swap. DAC1_MIX[1: DAC1_ZC DAC1 Loop-Back DAC1 Invert Signal Polarity DAC1 OUTA ---------- - 2 R CS42324 Mode Changes to affect immediately Zero Cross enabled Soft Ramp enabled Soft Ramp and Zero Cross enabled DAC1 OUTB ---------- - 2 L DS721A6 ...
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... DAC2 De-Emphasis Control DAC2 Single Volume Control DAC2 Soft Ramp Control DAC2_ZC Changes to affect immediately Zero Cross enabled Soft Ramp enabled Soft Ramp and Zero Cross enabled CS42324 2 1 DAC2_INV DAC2_MIX1 DAC2_MIX0 μ s digital de-emphasis filter response for a Mode 0 ...
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... AIN Pair 2 011 AIN Pair 3 100 AIN Pair 4 101 AIN Pair 5 110 DAC1 Output Pair 111 DAC2 Output Pair 56 DAC2 Loop-Back DAC2 Invert Signal Polarity DAC2 OUTA ---------- - Reserved MUTEC1 Output on MUTEC1 pin AOUT1 Source CS42324 DAC2 OUTB ---------- - AOUT1_SEL2 AOUT1_SEL1 AOUT1_SEL0 DS721A6 0 ...
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... This bit controls the logic state of the corresponding MUTEC3 pin. Though this bit is active high, it should be noted that the MUTEC3 pin is active low. MUTEC3 0 High (Mute Disengaged) 1 Low (Mute Engaged) DS721A6 Reserved MUTEC2 Output on MUTEC2 pin AOUT2 Source Reserved MUTEC3 Output on MUTEC3 pin CS42324 2 1 AOUT2_SEL2 AOUT2_SEL1 AOUT2_SEL0 2 1 AOUT3_SEL2 AOUT3_SEL1 AOUT3_SEL0 ...
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... AOUT3 Source ADCx_VOL4 ADCx_VOL3 Volume Setting +12.0 dB -84.0 dB Reserved Volume Setting -0.5 dB -1.0 dB -127.5 dB CS42324 2 1 ADCx_VOL2 ADCx_VOL1 ADCx_VOL0 ··· 0.0 dB -0.5 dB -1.0 dB ··· ··· DS721A6 ...
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... Interrupt Mode Setting Rising-edge Active Falling-edge Active Level Active Reserved DAC1_ SP2_ AMUTERM CLKERRM “Interrupt Status (Address 18h) (Read Only)” reg- Bit in Interrupt Register Not Masked Masked CS42324 -0.5 dB -1.0 dB ··· ADC_ OVFLx1 OVFLx0 SP2_CLKERR SP1_CLKERR 2 1 SP1_ ...
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... Mode (Address 16h)” register on “Interrupt Mode (Address 16h)” register on “Interrupt Mode (Address 16h)” register on “Interrupt Mode (Address 16h)” register on “Interrupt Mode (Address 16h)” register on page “Interrupt Mode (Address 16h)” register on page CS42324 59. If 59. If DS721A6 ...
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... If the ADC_OVFLNM bit is set, the ADC_OVFLN condition is masked DAC1_ SP2_ AMUTER CLKERR Bit in Interrupt Register Interrupt has not occurred since the last read of this register. Interrupt has occurred since the last read of this register. CS42324 “Interrupt Mode (Ad- “Interrupt Mode (Ad SP1_ ADC_ ADC_ CLKERR OVFLP OVFLN “ ...
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... This bit is read only. When set, indicates that a positive over-range condition occurred anywhere in the CS42324 ADC signal path and has ADC data has been clipped to positive full scale since the last read of this register. This interrupt bit is an edge-triggered event and will be cleared following a read of this reg- ister ...
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... This bit is read only. When set, indicates that a negative over-range condition occurred anywhere in the CS42324 ADC signal path and has ADC data has been clipped to negative full scale since the last read of this register. This interrupt bit is an edge-triggered event and will be cleared following a read of this register ...
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... In this case, no additional devices should be powered from VD. Power supply decoupling capacitors should be as near to the CS42324 as possible, with the low value ceramic ca- pacitor being the nearest. All signals, especially clocks, should be kept away from the FILT+, VCM_ADC, VBIAS, VCMBUF, and VCMDAC pins in order to avoid unwanted coupling into the modulators. The FILT+, VCM_ADC, VBIAS, VCMBUF, and VCMDAC decoupling capacitors, particularly the 0.1 µ ...
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... Figure 28. Double-Speed Mode Transition Band CS42324 0.52 0.54 0.56 0.58 0.60 Frequency (norm alized to Fs) 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 Frequency (norm alized to Fs) ...
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... Figure 29. Double-Speed Mode Transition Band (Detail) 66 0.10 0.08 0.06 0.04 0.02 0.00 -0.02 -0.04 -0.06 -0.08 -0.10 0.50 0.51 0.52 0.00 0.05 Figure 30. Double-Speed Mode Passband Ripple CS42324 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 Frequency (norm alized to Fs) DS721A6 ...
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... Figure 34. Single-Speed Passband Ripple 100 120 0.4 0.42 0.8 0.9 1 Figure 36. Double-Speed Transition Band CS42324 0.44 0.46 0.48 0.5 0.52 0.54 0.56 0.58 Frequency(normalized to Fs) 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 Frequency(normalized to Fs) 0.44 ...
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... Figure 40. Quad-Speed Transition Band 0.2 0.15 0.1 0.05 0 0.05 0.1 0.15 0.2 0 0.52 0.53 0.54 0.55 Figure 42. Quad-Speed Passband Ripple CS42324 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 Frequency(normalized to Fs) 0.3 0.4 0.5 0.6 0.7 Frequency(normalized to Fs) 0.05 0.1 ...
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... The deviation from the nominal full-scale analog output for a full-scale digital input. Gain Drift The change in gain value with temperature. Units in ppm/°C. Offset Error The deviation of the mid-scale transition (111...111 to 000...000) from the ideal. Units in mV. DS721A6 CS42324 69 ...
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... Symbol θ multi-layer JA θ dual-layer JA θ JC CS42324 A A1 MILLIMETERS MIN NOM MAX --- 1.40 1.60 0.05 0.10 0.15 0.17 0.22 0.27 8.70 9.0 BSC 9.30 6.90 7.0 BSC 7 ...
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... I² registered trademark of Philips Semiconductor. SPI is a trademark of Motorola, Inc. DS721A6 Pb-Free Grade Temp Range Yes Commercial -40°C to +85° C Yes Automotive -40°C to +105° Changes CS42324 Container Order # Tray CS42324-CQZ Tray CS42324-DQZ - CDB42324 page 8. 71 ...