CS42516-DQZR Cirrus Logic Inc, CS42516-DQZR Datasheet - Page 53

• Manufacturer Part Number: CS42516-DQZR
• Description: IC CODEC S/PDIF RCVR 64-LQFP
• Manufacturer: Cirrus Logic Inc
• Type: Audio Codecr

Specifications of CS42516-DQZR

• Package / Case: 64-LQFP
• Data Interface: Serial
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 2 / 6
• Sigma Delta: Yes
• Dynamic Range, Adcs / Dacs (db) Typ: 114 / 110
• Voltage - Supply, Analog: 4.75 V ~ 5.25 V
• Voltage - Supply, Digital: 3.13 V ~ 5.25 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Number Of Adc Inputs: 2
• Number Of Dac Outputs: 6
• Conversion Rate: 192 KSPs
• Interface Type: Serial (I2C, SPI)
• Resolution: 24 bit
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Number Of Channels: 2 ADC, 6 DAC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1502 - BOARD EVAL FOR CS42518 CODEC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

DS583F1
6.7
6.7.1
6.7.2
6.7.3
6.7.4
RMCK_DIV1
7
Clock Control (address 06h)
RMCK DIVIDE (RMCK_DIVX)
OMCK FREQUENCY (OMCK FREQX)
PLL LOCK TO LRCK (PLL_LRCK)
MASTER CLOCK SOURCE SELECT (SW_CTRLX)
Default = 00
Function:
Default = 00
Function:
Default = 0
0 - Disabled
1 - Enabled
Function:
Default = 00
Function:
When enabled, the internal PLL of the CS42516 will lock to the SAI_LRCK of the SAI serial port.
Divides/multiplies the internal MCLK, either from the PLL or OMCK, by the selected factor.
Sets the appropriate frequency for the supplied OMCK.
These two bits, along with the UNLOCK bit in register
on page
are set to '00'b, selecting the output of the PLL as the internal clock source, and the PLL becomes
unlocked, RMCK will equal OMCK, but all internal and serial port timings are not valid.
When the FRC_PLL_LK bit is set to ‘1’b, the SW_CTRLX bits must be set to ‘00’b. If the PLL becomes
RMCK_DIV0
OMCK Freq1 OMCK Freq0
6
63, determine the master clock source for the CS42516. When SW_CTRL1 and SW_CTRL0
0
0
1
1
OMCK Freq1
RMCK_DIV1 RMCK_DIV0
5
0
0
1
1
Table 11. OMCK Frequency Settings
0
1
0
1
Table 10. RMCK Divider Settings
OMCK Freq0
11.2896 MHz or 12.2880 MHz
16.9344 MHz or 18.4320 MHz
22.5792 MHz or 24.5760 MHz
Reserved
4
0
1
0
1
PLL_LRCK
Multiply by 2
Description
Divide by 1
Divide by 2
Divide by 4
3
Description
“Interrupt Status (address 20h) (Read Only)”
SW_CTRL1
2
SW_CTRL0
1
FRC_PLL_LK
CS42516
0
53