CS42325-CQZ Cirrus Logic Inc, CS42325-CQZ Datasheet - Page 54

• Manufacturer Part Number: CS42325-CQZ
• Description: IC CODEC STEREO AUDIO 48-LQFP
• Manufacturer: Cirrus Logic Inc
• Type: Audio Codecr

Specifications of CS42325-CQZ

• Package / Case: 48-LQFP
• Data Interface: Serial
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 1 / 2
• Sigma Delta: Yes
• Dynamic Range, Adcs / Dacs (db) Typ: 95 / 100
• Voltage - Supply, Analog: 3.13 V ~ 3.47 V
• Voltage - Supply, Digital: 3.13 V ~ 3.47 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Number Of Adc Inputs: 1
• Number Of Dac Outputs: 2
• Conversion Rate: 96 KSPS
• Interface Type: Serial (I2C, SPI)
• Resolution: 24 bit
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Number Of Channels: 1 ADC/2 DAC
• Supply Current: 10 mA to 24 mA
• Thd Plus Noise: - 88 dB ADC / - 90 dB DAC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

54
6.10.4 DAC1 Zero Cross Control
6.10.5 DAC1 Loop-Back
6.10.6 DAC1 Invert Signal Polarity
6.10.7 DAC1 Channel Mixer
Zero Cross Enable dictates that signal level changes, either by attenuation changes or muting, will occur
on a signal zero crossing to minimize audible artifacts. The requested level change will occur after a time-
out period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample rate) if the signal
does not encounter a zero crossing. The zero cross function is independently monitored and implemented
for each channel.
Soft Ramp and Zero Cross Enable
Soft Ramp and Zero Cross Enable dictate that signal level changes, either by attenuation changes or mut-
ing, will occur in 1/8 dB steps and be implemented on a signal zero crossing. The 1/8 dB level change will
occur after a time-out period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sam-
ple rate) if the signal does not encounter a zero crossing. The zero cross function is independently mon-
itored and implemented for each channel.
Loops ADC SDOUT, SCLK, and LRCK to DAC1 serial port pins.
When enabled, this bit will effect a 180 degree phase shift in the DAC1 channels.
These bits implement mono mixes of the left and right channels as well as a left/right channel swap.
0
0
1
1
0
1
0
1
00
01
10
11
DAC1_LOOP_
DAC1_INV
BACK
DAC1_MIX[1:0]
DAC1_SOFT
Off
On
Off
On
0
1
0
1
L
R
L
---------- -
+
2
R
DAC1 OUTA
DAC1 Invert Signal Polarity
DAC1_ZC
DAC1 Loop-Back
Changes to affect immediately
Zero Cross enabled
Soft Ramp enabled
Soft Ramp and Zero Cross enabled
R
L
L
---------- -
+
2
R
DAC1 OUTB
Mode
CS42325
DS838A2