CS4271-DZZ Cirrus Logic Inc, CS4271-DZZ Datasheet - Page 24

• Manufacturer Part Number: CS4271-DZZ
• Description: IC CODEC 24BIT 114DB 28-TSSOP
• Manufacturer: Cirrus Logic Inc
• Type: Stereo Audior

Specifications of CS4271-DZZ

• Data Interface: Serial
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 2 / 2
• Sigma Delta: Yes
• Dynamic Range, Adcs / Dacs (db) Typ: 108 / 114
• Voltage - Supply, Analog: 4.75 V ~ 5.25 V
• Voltage - Supply, Digital: 3.1 V ~ 5.25 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-TSSOP
• Audio Codec Type: Stereo
• No. Of Adcs: 2
• No. Of Dacs: 2
• No. Of Input Channels: 3
• No. Of Output Channels: 3
• Adc / Dac Resolution: 24bit
• Sampling Rate: 200kSPS
• Ic Interface Type: I2C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1003 - EVAL BOARD CS4271 STEREO CODEC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

5. APPLICATIONS
5.1
5.1.1
1) When using the CS4271 with an external MCLK, hold RST low until the power supply, MCLK, and LRCK are
2) Bring RST high. If the internally generated MCLK is being used, it will appear on the MCLK pin prior to 1 ms from
5.1.2
The CS4271 supports operation in either Master Mode or Slave Mode.
In Master Mode, LRCK and SCLK are outputs and are synchronously generated on-chip. LRCK is equal to Fs and
SCLK is equal to 64x Fs.
In Slave Mode, LRCK and SCLK are inputs, requiring external generation that is synchronous to MCLK. It is recom-
mended that SCLK be 64x Fs to maximize system performance.
In Stand-Alone Mode, the CS4271 will default to Slave Mode. Master Mode may be accessed by placing a 47 kΩ
pull-up to VL on the SDOUT (M/S) pin.
Configuration of clock ratios in each of these modes will be outlined in the Tables 3 and 4.
5.1.3
The CS4271 will operate at sampling frequencies from 4 kHz to 200 kHz. This range is divided into three speed
modes as shown in Table 1 below.
5.1.3.1
An external crystal may be used in conjunction with the CS4271 to generate the master clock signal. To accomplish
this, a 20 pF fundamental mode parallel resonant crystal must be connected between the XTI and XTO pins as
shown in the Typical Connection Diagram on page 23. This crystal must oscillate at the frequency shown in Table 2.
In this configuration, MCLK is a buffered output and, as shown in the Typical Connection Diagram, nothing other
than the crystal and its load capacitors should be connected to XTI and XTO. The MCLK signal will appear on the
MCLK pin prior to 1 ms from the release of RST.
To operate the CS4271 with an externally generated MCLK signal, no crystal should be used, XTI should be con-
nected to ground and XTO should be left unconnected. In this configuration, MCLK is an input and must be driven
externally with an appropriate speed clock.
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stable. When using the CS4271 with internally generated MCLK, hold RST low until the power supply is stable.
the release of RST.
Stand-Alone Mode
Recommended Power-Up Sequence
Master/Slave Mode
System Clocking
Crystal Applications (XTI/XTO)
Double Speed
Double Speed
Single Speed
Single Speed
Quad Speed
Quad Speed
Mode
Mode
Table 2. Crystal Frequencies
Table 1. Speed Modes
Sampling Frequency
Crystal Frequency
100-200 kHz
50-100 kHz
512 x Fs
256 x Fs
128 x Fs
4-50 kHz
CS4271
DS592F1