SI3000-KS Silicon Laboratories Inc, SI3000-KS Datasheet
SI3000-KS
Specifications of SI3000-KS
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SI3000-KS Summary of contents
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... Modem Voice Channel (DSVD) ! Telephony Description The Si3000 is a complete voice band audio codec solution that offers high integration by incorporating programmable input and output gain/ attenuation, a microphone bias circuit, handset hybrid circuit, and an output drive for 32 headphones. The Si3000 can be connected directly to the Si3034, Si3035, and Si3044 ISOcap North American and international DAA chipsets through its daisy-chaining serial interface ...
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Rev. 1.1 ...
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... Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Pre-amp/Microphone Bias Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Programmable Input Gain/Attenuation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Analog Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Programmable Output Gain/Attenuation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Line Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Speaker Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Digital Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Clock Generation Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Loopback Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Reducing Power-on Pop Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Rev. 1.1 Si3000 Page 3 ...
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... Typical values apply at nominal supply voltages and an operating temperature of 25°C unless otherwise stated. 2. The digital supply, V and analog supply 3.3 V logic when operating from 3 The Si3000 specifications are guaranteed using the typical application circuit (including component tolerance) of Figure 13. Table 2. DC Characteristics ±5 ± ...
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... DACTHD VIN=1 kHz,–6 dB,LINEO,600 VIN=1 kHz,–6 dB, SPKR, 60 VIN=1 kHz,–6 dB, HDST, 600 DACTHD VIN=1 kHz,–3 dB,LINEO,600 VIN=1 kHz,–3 dB, SPKR, 60 VIN=1 kHz,–3 dB, HDST, 600 V RX Rev. 1.1 Si3000 Min Typ Max Unit — 16 — Bits 80 84 — ...
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... Output starts clipping with half of full scale digital input, which corresponds to a 0.5 V Table 5. Absolute Maximum Ratings Parameter DC Supply Voltage Input Current, Si3000 Digital Input Pins Digital Input Voltage Operating Temperature Range Storage Temperature Range Note: Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation should be restricted to the conditions as specified in the operational sections of this data sheet ...
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... IL 2. The minimum RESET pulse width is the greater MCLK cycle times. MCLK RESET Figure 1. General Inputs Timing Diagram = 20 pF) L Symbol Test Condition dty Rev. 1.1 Si3000 Min Typ Max Unit 16.67 — — — — — — 250 — — – ...
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Table 7. Switching Characteristics—Serial Interface ( ±5% or 3.3 V ±10 70°C for K-grade Parameter Cycle Time, SCLK SCLK Duty Cycle Delay Time, SCLK to ...
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... K-Grade) A Symbol Min Typ F 0 — (3 dB) F 0.01 — (3 dB) –0.2 — — 4.4 –40 — t — 1.6/Fs gd Rev. 1.1 Si3000 Max Unit 3.6 kHz 3.6 kHz 0.1 dB — kHz — dB — sec Max Unit 3.6 kHz 3.6 kHz 0.2 dB — ...
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Input Frequency - Hz Figure 3. FIR Receive Filter Response Input Frequency - Hz Figure 4. FIR Receive Filter Passband Ripple For Figures 3–6, all filter plots apply to a sample rate ...
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... Figure 7. IIR Receive Filter Response Input Frequency - Hz Figure 8. IIR Receive Filter Passband Ripple Input Frequency - Hz Figure 9. IIR Transmit Filter Response Input Frequency - Hz Figure 10. IIR Transmit Filter Passband Ripple Input Frequency - Hz Figure 11. IIR Receive Group Delay Input Frequency - Hz Figure 12. IIR Transmit Group Delay Rev. 1.1 Si3000 11 ...
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... Figure 13. Si3000 Typical Application Circuit ...
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... Table 10. Component Values—Typical Application C2,C4,C5,C7,C9,C10 Symbol Value C1,C3,C6,C8 0.1 µ ±20% 10 µ ±20% D1 Motorola MMBD914L J1,J2 Phonejack Stereo JP1 4 Header K1 Relay DPDT L1,L2 Ferrite Bead 2.2 k, 1/4 W, ± 1/16 W, ±5% R11,R12 30 , 1/16 W, ±5% U2 LM317LZ Q1 PNP Transistor Rev. 1.1 Si3000 5% ± 5% ± 5% ± 13 ...
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... D/A converter. The DAC output is provided to a line output, a headphone drive output, and a handset output. Control for the various functions available on the Si3000 as well as the audio data are communicated to the device over a serial interface. The Si3000 can be connected directly to the Si3035, ...
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... On Primary Frames receives (Si3000 to DSP), the Si3000 drives SDO with 16-bits of audio data, if the Si3000 is in either Serial Mode However, if the Si3000 is in SLAVE mode (Mode 2), the Si3000 supplies 15-bits of Audio Data to the DSP and always drives the LSB zero. ...
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Primary FSYNC D15-D1 D0=1 (Software FC Bit) SDI XMT Data SDO RCV Data 16 SCLKS 128 SCLKs FSYNC (mode 0) FSYNC (mode 1) SDI High Z SDO Figure 16. Secondary Communication Data Format—Write Cycle 16 Primary ...
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... N1 8 bits Figure 18. Clock Generation Subsystem (PLL) Clock Generation Subsystem The Si3000 contains an on-chip clock generator. Using a single MCLK input frequency, the Si3000 can generate all the desired standard modem sample rates, as well as the common 11.025 kHz rate for audio playback. ...
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... Set the Power Down bit (PDN, register 6, bit 3). 2. MCLK may stay active or stop. 3. Restore MCLK before initiating the power up sequence. 4. Reset the Si3000 using the RESET pin (after MCLK is present). 5. Program the registers to desired settings. Rev. 1.1 = ...
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... To minimize power-on pop during initialization, a waiting period is recommended before powering up the analog output drivers. The waiting period starts when the reset signal to the Si3000 is negated. The wait time required is dependent on the external load. Typically, the load consists coupling capacitor in series with an equivalent load resistor to ground ...
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Control Registers Note: Any register not listed here is reserved and should not be written. Any register bit labelled reserved should be written to zero during writes to the register. Register 0 can be read (always ...
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... HPD Handset Drive Power Down Normal operation 0 = Power down handset driver. 1 MPD MIC Bias Power Down Power down MIC bias buffer Normal operation 0 CPD Chip Power Down Puts Si3000 into power down mode Normal operation SPD LPD HPD MPD R/W R/W ...
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Register 2. Control 2 Bit Name HPFD Type R/W tings = 0000_0000 Reset Set Bit Name 7:5 Reserved Read returns zero. 4 HPFD High Pass Filter (HPF) Disable HPF disabled ...
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... N1 N1. Contains the (value – 1) for determining the output frequency on PLL. Register 4. PLL1 Multiply M1 Bit Name Multiplier M1 Type R/W Reset settings = 0000_0000 Bit Name 7:0 M1 M1. Contains the (value – 1) for determining the output frequency on PLL Function Function Rev. 1.1 Si3000 23 ...
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Register 5. RX Gain Control 1 Bit Name LIG LIM MCG Type R/W R/W R/W Reset settings = 0100_0111 Bit Name 7:6 LIG Line in Gain gain 10 ...
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... Reset settings = 0101_1100 Bit Name 7 Reserved Read returns zero. 6:2 RXG RX PGA Gain Control. 11111 = 12 dB 10111 = 0 dB 00000 = –34.5 dB LSB = 1 LOM Line Out Mute Mute 1 = Active 0 HOM Handset Out Mute Mute 1 = Active LOM HOM R/W R/W Function Rev. 1.1 Si3000 25 ...
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Register 7. DAC Volume Control Bit Name TXG Type R/W Reset settings = 0101_1100 Bit Name 7 Reserved Read returns zero. 6:2 TXG TX PGA Gain Control. 11111 = 12 dB 10111 ...
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... Line Output analog attenuation on Line Output. Speaker Out Attenuation. 2:0 SOT 11 = –18 dB analog attenuation on Speaker Output –12 dB analog attenuation on Speaker Output –6 dB analog attenuation on Speaker Output analog attenuation on Speaker Output Function LOT SOT R/W R/W Type Rev. 1.1 Si3000 27 ...
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... Line level input with selectable gain dB. The full scale input level RMS 12 V Digital Supply Voltage. D Provides the digital supply voltage to the Si3000. Nominally either Analog Supply Voltage. A Provides the analog supply voltage to the Si3000. Nominally either SPKRR 16 SPKRL 2 MBIAS 15 LINEO HDST 3 ...
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... Pin # Pin Name 14 GND Ground. Connects to the system digital ground. 15 LINEO Line Output. Line level analog output with SPKRL Speaker Left Output. Analog output capable of driving a 60 Description full scale output level. RMS load. Rev. 1.1 Si3000 29 ...
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... Ordering Guide Part Number Si3000-KS 30 Table 14. Ordering Guide Package Temperature 16-pin SOIC 0°C to 70°C Rev. 1.1 ...
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... Package Outline Figure 19 illustrates the package details for the Si3000. Table 15 lists the values for the dimensions shown in the illustration. Figure 19. 16-pin Small Outline Plastic Package (SOIC) 7 Table 15. Package Diagram Dimensions Controlling Dimension: MM Symbol Inches Millimeters Min Max Min 0.053 0.069 1 ...
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Document Changes from Revision 1.0 to Revision 1.1 ! Updated Functional Block Diagram. ! Removed all B-grade references. ! Updated Table 4 (AC Characteristics). ! Updated Figure 14. ! Removed analog loopback feature description. 32 Rev. ...
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... Rev. 1.1 Si3000 33 ...
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Rev. 1.1 ...
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... Rev. 1.1 Si3000 35 ...
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