SI3000-C-FS Silicon Laboratories Inc, SI3000-C-FS Datasheet

IC VOICE CODEC 3.3V/5V 16SOIC

SI3000-C-FS

Manufacturer Part Number
SI3000-C-FS
Description
IC VOICE CODEC 3.3V/5V 16SOIC
Manufacturer
Silicon Laboratories Inc
Type
Voice-Band Codecr
Datasheet

Specifications of SI3000-C-FS

Package / Case
16-SOIC (0.154", 3.90mm Width)
Data Interface
Serial
Resolution (bits)
16 b
Number Of Adcs / Dacs
1 / 1
Sigma Delta
No
Dynamic Range, Adcs / Dacs (db) Typ
84 / 84
Voltage - Supply, Analog
3 V ~ 5.25 V
Voltage - Supply, Digital
3 V ~ 5.25 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Number Of Adc Inputs
3
Number Of Dac Outputs
2
Conversion Rate
12 KSPs
Resolution
16 bit
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
0 C
Number Of Channels
1 ADC, 1 DAC
Single Supply Voltage (typ)
3.3/5V
Single Supply Voltage (min)
3V
Single Supply Voltage (max)
5.25V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
336-1382
SI3000-C-FS

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
SI3000-C-FS
Manufacturer:
Exar
Quantity:
40
Part Number:
SI3000-C-FS
Manufacturer:
SILICON LABS/芯科
Quantity:
20 000
Part Number:
SI3000-C-FSR
Manufacturer:
SILICON
Quantity:
17 315
V
Features
Complete voice codec solution includes the following:
Applications
Description
The Si3000 is a complete voice band audio codec solution that offers high
integration by incorporating programmable input and output gain/
attenuation, a microphone bias circuit, handset hybrid circuit, and an
output drive for 32  headphones. The Si3000 can be connected directly
to the Si3034, Si3035, Si3044, and Si3056 North American and
international DAA chipsets through their daisy-chaining serial interface. It
also serves as a companion chip to a FAT ISOmodem chipset with voice
features, providing hardware support for a handset and speaker phone.
The device operates from a single 3.3 to 5 V power supply and is
available in a 16-pin small outline package (SOIC).
Functional Block Diagram
Rev. 1.4 12/10
OICE
84 dB ADC Dynamic Range
84 dB DAC Dynamic Range
4–12 kHz Sample Rates
30 dB Microphone Pre-Amp
Programmable Input Gain/
Attenuation: –34.5 dB to 12 dB
Programmable Output Gain/
Attenuation: –34.5 dB to 12 dB
Modem Voice Channel (DSVD)
Telephony
RESET
FSYNC
MCLK
SCLK
SDO
SDI
B
AND
Interface
Digital
C
Prog Gain/
Attenuator
Prog Gain/
Attenuator
ODEC W I T H
Si3000
ADC
DAC
Copyright © 2010 by Silicon Laboratories
Support for 32  Headphones
3:1 Analog Input Mixer
3.3–5.0 V Power Supply
Direct Serial Interface to DSPs
Direct Connection to Si303x/44/56,
serial interface DAA chipsets
Low profile 16-Pin SOIC Package
RoHS-compliant package
available
Speech Processing
General Purpose Analog I/O
Companion chip for FDX
ISOmodems with voice features
Handset
Hybrid
0/+10/+20/+30 dB
0/+10/+20 dB
Headphone
0/–6/–12/–18 dB
Driver
0/–6/–12/–18 dB
M
ICROPHONE
MBIAS
MIC
LINEI
HDST
SPKRR
SPKRL
LINEO
/S
FSYNC
SPKRR
MBIAS
MCLK
HDST
SCLK
P E A K E R
SDO
SDI
Ordering Information:
Pin Assignments
See page 29.
1
2
3
4
5
6
7
8
Si3000
Si3000
16
15
14
13
12
11
10
9
D
RIVE
LINEO
SPKRL
GND
V
V
LINEI
MIC
RESET
A
D
Si3000

Related parts for SI3000-C-FS

SI3000-C-FS Summary of contents

Page 1

... Telephony  Description The Si3000 is a complete voice band audio codec solution that offers high integration by incorporating programmable input and output gain/ attenuation, a microphone bias circuit, handset hybrid circuit, and an output drive for 32  headphones. The Si3000 can be connected directly to the Si3034, Si3035, Si3044, and Si3056 North American and international DAA chipsets through their daisy-chaining serial interface ...

Page 2

... Si3000 2 Rev. 1.4 ...

Page 3

... Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 4. Pin Descriptions: Si3000 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 5. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6. Package Outline: 16-Pin SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7. 16-Pin SOIC Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 8. Package Markings (Top Markings .32 8.1. Si3000-C-GS Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 8.2. Si3000-C-FS Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 Rev. 1.4 Si3000 Page 3 ...

Page 4

... Typical values apply at nominal supply voltages and an operating temperature of 25°C unless otherwise stated. 2. The digital supply, V and analog supply 3.3 V logic when operating from 3 The Si3000 specifications are guaranteed using the typical application circuit (including component tolerance) of Figure 13. Table 2. DC Characteristics ± ...

Page 5

... VIN=1 kHz,–6 dB,LINEO,600  DACTHD VIN=1 kHz,–6 dB, SPKR, 60  VIN=1 kHz,–6 dB, HDST, 600  VIN=1 kHz,–3 dB,LINEO,600  DACTHD VIN=1 kHz,–3 dB, SPKR, 60  VIN=1 kHz,–3 dB, HDST, 600  Rev. 1.4 Si3000 Min Typ Max Unit — 16 — Bits 80 84 — ...

Page 6

... With a 600  load. Output starts clipping with half of full scale digital input, which corresponds to a 0.5 V Table 5. Absolute Maximum Ratings Parameter DC Supply Voltage Input Current, Si3000 Digital Input Pins Digital Input Voltage Operating Temperature Range Storage Temperature Range Note: Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation should be restricted to the conditions as specified in the operational sections of this data sheet ...

Page 7

... The minimum RESET pulse width is the greater of 5  MCLK cycle times. MCLK RESET Figure 1. General Inputs Timing Diagram = 20 pF) L Symbol Test Condition dty Rev. 1.4 Si3000 Min Typ Max Unit 16.67 — — — — — — 250 — — ns — ...

Page 8

... Si3000 Table 7. Switching Characteristics—Serial Interface ( ±5% or 3.3 V ±10 70° Parameter Cycle Time, SCLK SCLK Duty Cycle Delay Time, SCLK to FSYNC  Delay Time, SCLK  to SDO Valid Delay Time, SCLK to FSYNC  Setup Time, SDI, before SCLK  ...

Page 9

... A Symbol Min Typ F 0 — (3 dB) F 0.01 — (3 dB) –0.2 — — 4.4 –40 — t — 1.6/Fs gd Rev. 1.4 Si3000 Max Unit 3.6 kHz 3.6 kHz 0.1 dB — kHz — dB — sec Max Unit 3.6 kHz 3.6 kHz 0.2 dB — ...

Page 10

... Si3000 Input Frequency - Hz Figure 3. FIR Receive Filter Response Input Frequency - Hz Figure 4. FIR Receive Filter Passband Ripple For Figures 3–6, all filter plots apply to a sample rate of  kHz. The filters scale with the sample rate as follows: where Fs is the sample frequency. ...

Page 11

... Figure 7. IIR Receive Filter Response Input Frequency - Hz Figure 8. IIR Receive Filter Passband Ripple Input Frequency - Hz Figure 9. IIR Transmit Filter Response Input Frequency - Hz Figure 10. IIR Transmit Filter Passband Ripple Input Frequency - Hz Figure 11. IIR Receive Group Delay Input Frequency - Hz Figure 12. IIR Transmit Group Delay Rev. 1.4 Si3000 11 ...

Page 12

... Si3000 12 Rev. 1.4 ...

Page 13

... C1,C3,C6,C8 0.1 µ ±20% 10 µ ±20% D1 Motorola MMBD914L J1,J2 Phonejack Stereo JP1 4 Header K1 Relay DPDT L1,L2 Ferrite Bead 0 , 1 , 1 k, 1 2.2 k, 1/4 W, ±5% 10 , 1/16 W, ± , 1/16 W, ±5% R11,R12 U2 LM317LZ Q1 PNP Transistor Rev. 1.4 Si3000 5% ± 5% ± 5% ± 13 ...

Page 14

... D/A converter. The DAC output is provided to a line output, a headphone drive output, and a handset output. Control for the various functions available on the Si3000 as well as the audio data are communicated to the device over a serial interface. The Si3000 can be connected directly to the Si3035, ...

Page 15

... Primary Frames. Hence, no Primary Frames are dropped. On Primary Frame transmits (DSP to Si3000), the Si3000 treats the LSB (16th bit flag to request a Secondary Frame. Set the primary frame LSB = 1 to request a secondary frame; otherwise, set the primary frame LSB = 0. Therefore, out of 16-bits of transmit data on SDI, only 15-bits represent actual audio data ...

Page 16

... Si3000 Prim ary D 15 – (Softw are FC Bit ata ata 16 SCLKs 128 SCLKs ode ode Figure 16. Secondary Communication Data Format—Write Cycle ode ode igh Z Figure 17. Secondary Frame Format—Read Cycle 16 Secondary Prim ary Secondary ata U pdate Secondary ata U pdate 256 SCLKs Figure 15 ...

Page 17

... P D Figure 18. Clock Generation Subsystem (PLL) 2.9. Clock Generation Subsystem The Si3000 contains an on-chip clock generator. Using a single MCLK input frequency, the Si3000 can generate all the desired standard modem sample rates, as well as the common 11.025 kHz rate for audio playback. ...

Page 18

... Set the Power Down bit (PDN, register 6, bit 3). 2. MCLK may stay active or stop Restore MCLK before initiating the power up sequence. 4. Reset the Si3000 using the RESET pin (after MCLK is present). 5. Program the registers to desired settings. 2.11. Loopback Operation The ...

Page 19

... Table 13. Register Summary Bit 7 Bit 6 Bit 5 Bit 4 SR SPD HPFD Divider N1 Multiplier M1 LIG LIM MCG RXG TXG SLSC SRSC LOSC Rev. 1.4 Si3000 Bit 3 Bit 2 Bit 1 Bit 0 LPD HPD MPD CPD PLL DL1 DL2 MCM HIM IIR LOM HOM SLM SRM ...

Page 20

... Handset Drive Power Down. Normal operation 0 = Power down handset driver. 1 MPD MIC Bias Power Down. Power down MIC bias buffer. Normal operation Chip Power Down.  0 CPD 1 = Puts Si3000 into power down mode. Normal operation SPD LPD R/W R/W Function Rev ...

Page 21

... Enables digital loopback (DAC analog out ADC analog in Normal operation 1 DL2 Digital Loopback Enables digital loopback (DAC one bit ADC one bit Normal operation 0 Reserved Read returns zero HPFD PLL R/W R/W Function Rev. 1.4 Si3000 DL1 DL2 R/W R/W 21 ...

Page 22

... Si3000 Register 3. PLL1 Divide N1 Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 N1 N1. Contains the (value – 1) for determining the output frequency on PLL. Register 4. PLL1 Multiply M1 Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 M1 M1. Contains the (value – 1) for determining the output frequency on PLL. ...

Page 23

... Mute MIC input 0 = MIC input goes into mixer. 1 HIM Handset Input Mute Mute handset input 0 = Handset input goes into mixer. 0 IIR IIR Enable Enables IIR filter 0 = Enables FIR filter LIM MCG R/W R/W Function Rev. 1.4 Si3000 MCM HIM IIR R/W R/W R/W 23 ...

Page 24

... Si3000 Register 6. ADC Volume Control Bit D7 D6 Name Type Reset settings = 0101_1100 Bit Name 7 Reserved Read returns zero. 6:2 RXG RX PGA Gain Control. 11111 = 12 dB 10111 = 0 dB 00000 = –34.5 dB LSB = 1 LOM Line Out Mute Mute 1 = Active 0 HOM Handset Out Mute Mute ...

Page 25

... Reset settings = 0101_1100 Bit Name 7 Reserved Read returns zero. 6:2 TXG TX PGA Gain Control. 11111 = 12 dB 10111 = 0 dB 00000 = –34.5 dB LSB = 1 SLM SPKR_L Mute Mute 1 = Active 0 SRM SPKR_R Mute Mute 1 = Active TXG R/W Function Rev. 1.4 Si3000 SLM SRM R/W R/W 25 ...

Page 26

... Si3000 Register 8. Status Report Bit D7 D6 SLSC SRSC Name R R Type Reset settings = 0000_0000 Bit Name 7 SLSC SPK_L Short Circuit Indicate short circuit status is detected at left speaker Normal mode 6 SRSC SPK_R Short Circuit Indicate short circuit status is detected at right speaker Normal mode ...

Page 27

... V 11 LINEI Line Input. Line level input with selectable gain dB. The full scale input level RMS 12 V Digital Supply Voltage. D Provides the digital supply voltage to the Si3000. Nominally either 5 or 3.3 V and within 0 SPKRL SPKRR LINEO MBIA ...

Page 28

... Si3000 Pin # Pin Name 13 V Analog Supply Voltage. A Provides the analog supply voltage to the Si3000. Nominally either 5 or 3.3 V and within 0 GND Ground. Connects to the system digital ground. 15 LINEO Line Output. Line level analog output with SPKRL Speaker Left Output. Analog output capable of driving a 60  load. ...

Page 29

... Ordering Guide Part Number Si3000-C-FS Si3000-C-GS *Note: Add an “R” at the end of the device to denote tape and reel option. Table 14. Ordering Guide Package Lead-Free SOIC-16 Yes SOIC-16 Yes Rev. 1.4 Si3000 Temp. Range °C – °C 29 ...

Page 30

... Si3000 6. Package Outline: 16-Pin SOIC Figure 19 illustrates the package details for the Si3000. Table 15 lists the values for the dimensions shown in the illustration. Figure 19. 16-Pin Small Outline Integrated Circuit (SOIC) Package Table 15. Package Diagram Dimensions Dimension Min A — A1 0.10 A2 1. ...

Page 31

... SOIC Land Pattern Figure illustrates the recommended land pattern for the Si3000 16-pin SOIC. Table 16 lists the values for the dimensions shown in the illustration.   Figure 20. 16-Pin SOIC Land Pattern Diagram Table 16. 16-Pin MSOP Land Pattern Dimensions Dimension Notes: General 1 ...

Page 32

... Si3000 8. Package Markings (Top Markings) Codes for the Si3000-C-GS and Si3000-C-FS top marks are as follows Current Year  Work Week  Die Revision  TTTTT = Trace Code  8.1. Si3000-C-GS Top Marking   8.2. Si3000-C-FS Top Marking   32 Rev. 1.4 ...

Page 33

... Updated Figure 13 on page 12.  Updated "2.8. Digital Interface" on page 15.  Updated "2.11. Loopback Operation" on page 18.  Updated "4. Pin Descriptions: Si3000" on page 27.  Revision 1.3 to Revision 1.4 Added extended temperature Si3000-C-GS to Table  14 ordering guide. Added Section 7, 16-Pin SOIC Land Pattern. ...

Page 34

... Si3000 C I ONTACT NFORMATION Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Please visit the Silicon Labs Technical Support web page: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support request. ...

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