SI3000-C-FS Silicon Laboratories Inc, SI3000-C-FS Datasheet - Page 15

• Manufacturer Part Number: SI3000-C-FS
• Description: IC VOICE CODEC 3.3V/5V 16SOIC
• Manufacturer: Silicon Laboratories Inc
• Type: Voice-Band Codecr

Specifications of SI3000-C-FS

• Package / Case: 16-SOIC (0.154", 3.90mm Width)
• Data Interface: Serial
• Resolution (bits): 16 b
• Number Of Adcs / Dacs: 1 / 1
• Sigma Delta: No
• Dynamic Range, Adcs / Dacs (db) Typ: 84 / 84
• Voltage - Supply, Analog: 3 V ~ 5.25 V
• Voltage - Supply, Digital: 3 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Number Of Adc Inputs: 3
• Number Of Dac Outputs: 2
• Conversion Rate: 12 KSPs
• Resolution: 16 bit
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Number Of Channels: 1 ADC, 1 DAC
• Single Supply Voltage (typ): 3.3/5V
• Single Supply Voltage (min): 3V
• Single Supply Voltage (max): 5.25V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 336-1382; SI3000-C-FS

2.5. Programmable Output Gain/Attenuation
Prior to D/A conversion, the Si3000 contains a digital
programmable gain/attenuator which provides up to
12 dB of gain or –34.5 dB of attenuation in 1.5 dB steps.
Level changes only take effect on zero crossings to
minimize audible artifacts. The requested level change
is implemented if no zero crossing is found after 256
frames. Write the DAC Volume Control (register 7) to
set digital input gain/attenuation.
2.6. Line Output
LINEO is a line level analog output signal centered
around a common mode voltage. The minimum
recommended load impedance is 600 . This output is
a fully filtered output with a 1 Vrms full scale range. The
only external component required is the 10 F DC
blocking capacitor shown in Figure 13 on page 12. This
output may be muted through the LOM bit in register 6
or attenuated by setting the analog attenuation bits in
register 9.
2.7. Speaker Output
The SPKRL and SPKRR are mono, in-phase, analog
outputs capable of driving a small loudspeaker whose
impedance is typically 32 (see Figure 13 on page 12).
The speaker outputs may be muted through the SLM
and SRM bits in the DAC Gain Control register 7 or
attenuated by setting the analog attenuation bits in
register 9.
2.8. Digital Interface
The Si3000 has two serial interface modes that support
most standard modem DSPs. These modes are
selected by the addition of a 50 k pull-down/up resistor
on the SDO and SCLK pins as shown in Figure 13 on
page 12. The key difference between these two serial
modes is the operation of the FSYNC signal. Table 11
summarizes the serial mode definitions.
The digital interface consists of a single synchronous
serial link which communicates audio and control data.
In slave mode, SCLK is connected only to the pullup/
pulldown resistor, and MCLK is a 256 Fs input which is
internally multiplied using the on-chip phase-locked loop
(PLL) to clock the A/D converter and D/A converter. In
master mode, the master clock (MCLK) is an input and
the serial data clock (SCLK) is an output. The MCLK
*Note: Pull-up/pull-down states
Mode
0
1
2
3
SCLK*
0
0
1
1
Table 11. Serial Modes
SDO*
0
1
0
1
FSYNC frames data
FSYNC pulse starts data frame
Slave mode
Reserved
Description
Rev. 1.4
frequency and the value of the sample rate control
registers 3 and 4 determine the sample rate (Fs). The
serial port clock, SCLK, runs at 256 bits per frame,
where the frame rate is equivalent to the sample rate.
Digital information is transferred between the DSP and
the Si3000 in the form of 16-bit Primary Frames and 16-
bit Secondary Frames. There are separate pins for
receive (SDO) and transmit (SDI) functions, providing
simultaneous receive/transmit operation within each
frame.
Primary Frames are used for digital audio data samples.
Primary Frames occur at the frame rate and are always
present.
Secondary Frames are used for accessing internal
Si3000 registers. Secondary Frames are not always
present
Secondary Frames are present, they occur mid-point
between Primary Frames. Hence, no Primary Frames
are dropped.
On Primary Frame transmits (DSP to Si3000), the
Si3000 treats the LSB (16th bit) as a flag to request a
Secondary Frame. Set the primary frame LSB = 1 to
request a secondary frame; otherwise, set the primary
frame LSB = 0. Therefore, out of 16-bits of transmit data
on SDI, only 15-bits represent actual audio data. When
secondary frames are not present, no transmission
occurs during this time slot.
On Primary Frames receives (Si3000 to DSP), the
Si3000 drives SDO with 16-bits of audio data, if the
Si3000 is in either Serial Mode 0 or 1. However, if the
Si3000 is in SLAVE mode (Mode 2), the Si3000
supplies 15-bits of Audio Data to the DSP and always
drives the LSB zero. This feature is designed to work
with the Si3021 register 14 SSEL set to 10. In this
system configuration, when the DSP receives Primary
Frames, it can check the LSB to determine whether the
receive data is from the Si3021 or from the Si3000.
On Secondary Frame receives and transmits; the
Si3000 treats the input and output serial stream as 16-
bits of data. Figure 15 shows the relative timing of the
serial frames.
Figure 16 and Figure 17 illustrate the secondary frame
write cycle and read cycle, respectively. During a read
cycle, the R/W bit is high and the 5-bit address field
contains the address of the register to be read. The
contents of the 8-bit control register are placed on the
SDO signal. During a write cycle, the R/W bit is low and
the 5-bit address field contains the address of the
register to be written. The 8-bit data to be written
immediately follows the address on SDI. Only one
register can be read or written during each secondary
frame. See "3. Control Registers" on page 19 for the
register addresses and functions.
and
are
requested
on-demand.
Si3000
When
15