KSZ8873RLL Micrel Inc, KSZ8873RLL Datasheet - Page 10

• Manufacturer Part Number: KSZ8873RLL
• Description: IC ETHERNET SWITCH 3PORT 64-LQFP
• Manufacturer: Micrel Inc

Specifications of KSZ8873RLL

• Data Rate: 100Mbps
• Controller Type: Ethernet Switch Controller
• Interface: RMII
• Voltage - Supply: 1.8V, 2.5V, 3.3V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• No. Of Ports: 3
• Ethernet Type: IEEE 802.3u
• Supply Current: 115mA
• Supply Voltage Range: 2.5V, 3.3V
• Digital Ic Case Style: LQFP
• No. Of Pins: 64
• Svhc: No SVHC (15-Dec-2010)
• Base: RoHS Compliant
• Number Of Primary Switch Ports: 3
• Internal Memory Buffer Size: 32
• Fiber Support: No
• Integrated Led Drivers: Yes
• Phy/transceiver Interface: MII
• Power Supply Type: Analog/Digital
• Data Rate (typ): 10/100Mbps
• Vlan Support: Yes
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Mounting: Surface Mount
• Jtag Support: No
• Operating Supply Voltage (max): 1.89/3.465V
• Operating Temperature Classification: Commercial
• Interface Type: MII, RMII
• Operating Temperature Range: 0°C To +70°C
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant
• Other names: 576-3461

Micrel, Inc.
KSZ8873MLL/FLL/RLL
List of Tables
Table 1. FX Signal Threshold.........................................................................................................................................18
Table 2. MDI/MDI-X Pin Definitions ...............................................................................................................................18
Table 3. Internal Function Block Status ..........................................................................................................................23
Table 4. MII Signals .......................................................................................................................................................28
Table 5. RMII Clock Setting ............................................................................................................................................29
Table 6. RMII Signal Description....................................................................................................................................30
Table 7. RMII Signal Connections..................................................................................................................................30
Table 8. MII Management Interface Frame Format .......................................................................................................31
Table 9. Serial Management Interface (SMI) Frame Format .........................................................................................31
Table 10. FID+DA Lookup in VLAN Mode .....................................................................................................................32
Table 11. FID+SA Lookup in VLAN Mode .....................................................................................................................32
Table 12. Spanning Tree States ....................................................................................................................................34
Table 13. SPI Connections ............................................................................................................................................39
Table 14. Data Rate Limit Table ....................................................................................................................................61
Table 15. Format of Static MAC Table (8 Entries) .........................................................................................................81
Table 16. Format of Static VLAN Table (16 Entries)......................................................................................................83
Table 17. Format of Dynamic MAC Address Table (1K Entries) ...................................................................................84
Table 18. Format of “Per Port” MIB Counters ................................................................................................................85
Table 19. Port 1’s “Per Port” MIB Counters Indirect Memory Offsets............................................................................86
Table 20. Format of “All Port Dropped Packet” MIB Counters.......................................................................................86
Table 21. “All Port Dropped Packet” MIB Counters Indirect Memory Offsets................................................................87
Table 22. EEPROM Timing Parameters ........................................................................................................................90
Table 23. MAC Mode MII Timing Parameters................................................................................................................91
Table 24. PHY Mode MII Timing Parameters ................................................................................................................92
Table 25. RMII Timing Parameters ................................................................................................................................93
Table 26. I2C Timing Parameters ..................................................................................................................................95
Table 27. SPI Input Timing Parameters.........................................................................................................................96
Table 28. SPI Output Timing Parameters ......................................................................................................................97
Table 29. Auto-Negotiation Timing Parameters.............................................................................................................98
Table 30. Reset Timing Parameters ..............................................................................................................................99
Table 31. Transformer Selection Criteria .....................................................................................................................101
Table 32. Qualified Single Port Magnetics...................................................................................................................101
Table 33. Typical Reference Crystal Characteristics ...................................................................................................101
September 2009
10
M9999-092309-1.2