DS3112+ Maxim Integrated Products, DS3112+ Datasheet - Page 42
![IC MUX TEMPE T3/E3 256-BGA](/photos/6/82/68222/406-256-bga_sml.jpg)
DS3112+
Manufacturer Part Number
DS3112+
Description
IC MUX TEMPE T3/E3 256-BGA
Manufacturer
Maxim Integrated Products
Datasheet
1.DS3112.pdf
(133 pages)
Specifications of DS3112+
Controller Type
Framer, Multiplexer
Interface
Parallel/Serial
Voltage - Supply
3.135 V ~ 3.465 V
Current - Supply
150mA
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
256-PBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Figure 4-5. HDLC Status Bit Flow
Transmit
Packet End
Signal from
HDLC
Internal Transmit
Low Water Mark
Signal from
HDLC
Internal Receive
High Water Mark
Signal from
HDLC
Internal Receive
Packet Start
Signal from
HDLC
Internal Receive
Packet End
Signal from
HDLC
Internal Transmit
FIFO Underrun
Signal from
HDLC
Internal Receive
FIFO Overrun
Signal from
HDLC
Internal Receive
Abort Detect
Signal from
HDLC
NOTE: ALL EVENT LATCHES ABOVE ARE CLEARED WHEN THE HSR REGISTER IS READ.
Event Latch
Event Latch
Event Latch
Event Latch
Event Latch
Event Latch
ROVR (IHSR Bit 13)
RHWM (IHSR Bit 4)
RABT (IHSR Bit 15)
TLWM (IHSR Bit 2)
TEND (IHSR Bit 0)
TUDR (IHSR Bit 3)
RPE (IHSR Bit 6)
RPS (IHSR Bit 5)
RHWM
(HSR Bit 4)
RPS
(HSR Bit 5)
RPE
(HSR Bit 6)
TUDR
(HSR Bit 7)
ROVR
(HSR Bit 13)
RABT
(HSR Bit 15)
TEND
(HSR Bit 0)
TLWM
(HSR Bit 2)
42 of 133
Mask
Mask
Mask
Mask
Mask
Mask
Mask
Mask
OR
HDLC
(IMSR Bit 3)
Mask
HDLC
Status Bit
(MSR Bit 3)
INT*
Hardware
Signal
DS3112
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