Z16C3220FSG Zilog, Z16C3220FSG Datasheet - Page 30
Z16C3220FSG
Manufacturer Part Number
Z16C3220FSG
Description
IC 20MHZ CMOS IUSC 80-QFP
Manufacturer
Zilog
Series
IUSC™r
Specifications of Z16C3220FSG
Controller Type
USC Controller
Interface
DMA
Voltage - Supply
4.5 V ~ 5.5 V
Current - Supply
7mA
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
80-BQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Manufacturer
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Z
PS97USC0200
ILOG
Address: 01001 (Shared)
Notes:
BDCR Controls the amount of time that DMA may remain bus master.
Bits 15 through 8 are used to select a limit for the number of DMA transfers on the Bus
while the DMA is bus master. This limit is a binary number, a value of zero disables
the transaction limit function.
Bits 7 through 0 are used to select a limit for the number of clock cycles that the DMA
may remain on the bus as bus master.
Bus transaction will always complete, even if the clock cycle limit is exceeded during
the bus cycle, and even if the cycle is extended by external hardware signalling
through /WAIT//RDY.
Figure 15. Burst Dwell Control Register (BDCR)
P R E L I M I N A R Y
Clock Cycle Limit (Bit 3)
Clock Cycle Limit (Bit 4)
Clock Cycle Limit (Bit 5)
Clock Cycle Limit (Bit 6)
Clock Cycle Limit (Bit 7)
Clock Cycle Limit (Bit 8)
Clock Cycle Limit (Bit 9)
Clock Cycle Limit (Bit 10)
Transaction Limit (Bit 0)
Transaction Limit (Bit 1)
Transaction Limit (Bit 2)
Transaction Limit (Bit 3)
Transaction Limit (Bit 4)
Transaction Limit (Bit 5)
Transaction Limit (Bit 6)
Transaction Limit (Bit 7)
Z16C32 IUSC
30
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