Z16C3510VSG Zilog, Z16C3510VSG Datasheet - Page 71

• Manufacturer Part Number: Z16C3510VSG
• Description: IC 10MHZ Z8500 CMOS ISCC 68-PLCC
• Manufacturer: Zilog
• Series: IUSC™r

Specifications of Z16C3510VSG

• Controller Type: Serial Communications Controller (SCC)
• Interface: USB
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 50mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 68-LCC (J-Lead)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

UM011001-0601
5.4.6 Write Register 5 (Transmit Parameter
and Controls)
WR5 contains control bits that affect the operation of the
transmitter. B2 affects both the transmitter and the receiv-
er. Bit positions for WR5 are shown in Figure 5-7.
Bit 7 is the Data Terminal Ready control bit
This is the control bit for the /DTR//REQ pin while the pin
is in the DTR mode (selected in WR14). When set, /DTR
is Low; when reset, /DTR is High. This bit is ignored when
/DTR//REQ is programmed to act as a /REQUEST pin.
This bit is reset by a channel or hardware reset. Refer to
the description of Bit 2 in Write Register 14.
Bits 6 and 5 are the Transmit Bits/Character select bits
1 and 0
These bits control the number of bits in each byte trans-
ferred to the transmit buffer. Bits sent must be right justified
with least significant bits first.
The Five Or Less mode allows transmission of one to five
bits per character; however, the CPU should format the data
character as shown below in Table 5-6. In the Six or Seven
Bits/Character modes, unused data bits are ignored.
Write Register 5
D7
D6
0
0
1
1
D5 D4 D3 D2 D1 D0
0
1
0
1
Tx 5 Bits(Or Less)/Character
Tx 7 Bits/Character
Tx 6 Bits/Character
Tx 8 Bits/Character
Figure 5-7. Write Register 5
Tx CRC Enable
RTS
/SDLC/CRC-16
Tx Enable
Send Break
DTR
P R E L I M I N A R Y
For five or less bits per character selection in WR5, the fol-
lowing encoding is used in the data sent to the transmitter.
D is the data bit(s) to be sent.
Bit 4 is the Send Break control bit
When set, this bit forces the TxD output to send continuous
“0s” beginning with the following transmit clock, regardless
of any data being transmitted at the time. This bit functions
whether or not the transmitter is enabled. When reset, TxD
continues to send the contents of the Transmit Shift regis-
ter, which might be syncs, data, or all “1s.” If this bit is set
while in the X21 mode (Monosync and Loop mode select-
ed) and character synchronization is achieved in the re-
ceiver, this bit is automatically reset and the transmitter be-
gins sending syncs or data. This bit can also be reset by a
channel or hardware reset.
Bit 3 is Transmit Enable
Data is not transmitted until this bit is set, and the TxD out-
put sends continuous “1s” unless Auto Echo mode or
SDLC Loop mode is selected. If this bit is reset after trans-
mission started, the transmission of data or sync charac-
ters is completed. If the transmitter is disabled during the
transmission of a CRC character, sync or flag characters
are sent instead of CRC. This bit is reset by a channel or
hardware reset.
This bit determines whether or not CRC is calculated on a
transmit character. If this bit is set at the time the character
is loaded from the transmit buffer to the Transmit Shift reg-
ister, CRC is calculated on that character. CRC is not au-
tomatically sent unless this bit is set when the transmit un-
derrun exists.
D7 D6 D5 D4 D3 D2 D1 D0 Description
1
1
1
1
0
Bit 7
1
1
1
0
0
0
0
1
1
Table 5-6. Transmit Bits per Character
1
1
0
0
0
D
1
0
0
0
Bit 6
D
D
0
0
0
0
1
0
1
D
D
D
0
0
Z16C35ISCC™ User’s Manual
Bits/Character
5 or less bits/character
7 bits/character
6 bits/character
8 bits/character
D
D
D
D
0
D Sends one data bit
D Sends two data bits
D Sends three data bits
D Sends four data bits
D Sends five data bits
Register Descriptions
5-11
5