DS3112+W Maxim Integrated Products, DS3112+W Datasheet - Page 20
![IC MUX T3/E3 3.3V 256-PBGA](/photos/6/82/68222/406-256-bga_sml.jpg)
DS3112+W
Manufacturer Part Number
DS3112+W
Description
IC MUX T3/E3 3.3V 256-PBGA
Manufacturer
Maxim Integrated Products
Datasheet
1.DS3112.pdf
(133 pages)
Specifications of DS3112+W
Controller Type
Framer, Multiplexer
Interface
Parallel/Serial
Voltage - Supply
3.135 V ~ 3.465 V
Current - Supply
150mA
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
256-PBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Signal Name:
Signal Description:
Signal Type:
This signal is an open-drain output that will be forced low if one or more unmasked interrupt sources
within the device is active. The signal will remain low until either the interrupt is serviced or masked.
Signal Name:
Signal Description:
Signal Type:
This active low signal must be asserted for the device to accept a read or write command from an external
host.
Signal Name:
Signal Description:
Signal Type:
This input signal controls a latch that exists on the CA0 to CA7 inputs. When CALE is high, the latch is
transparent. The falling edge of CALE causes the latch to sample and hold the CA0 to CA7 inputs. In
nonmultiplexed bus applications, CALE should be tied high. In multiplexed bus applications, CA[7:0]
should be tied to CD[7:0] and the falling edge of CALE will latch the address.
CINT
CPU Bus Interrupt
Output (Open Drain)
CCS
CPU Bus Chip Select
Input
CALE
CPU Bus Address Latch Enable
Input
20 of 133
DS3112
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