DS3148N Maxim Integrated Products, DS3148N Datasheet - Page 59
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DS3148N
Manufacturer Part Number
DS3148N
Description
IC 8CH DS3/3 FRAMER 349-BGA
Manufacturer
Maxim Integrated Products
Datasheet
1.DS3148.pdf
(89 pages)
Specifications of DS3148N
Controller Type
DS3/E3 Framer
Interface
LIU
Voltage - Supply
3.135 V ~ 3.465 V
Current - Supply
640mA
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
349-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Bit 7: Receive FIFO Overrun Latched (ROVRL). This latched status bit is set to 1 each time the receive FIFO
overruns. ROVRL is cleared when the host processor writes a 1 to it and is not set again until another overrun
occurs (i.e., the FIFO has been read from and then allowed to fill up again). When ROVRL is set, it can cause a
hardware interrupt to occur if the ROVRIE bit in the
both set to 1. The interrupt is cleared when this bit is cleared or one or both of the interrupt-enable bits are cleared.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 0: Transmit Packet-End Interrupt Enable (TENDIE). This bit enables an interrupt if the TENDL bit in the
HSRL
Bit 1: Transmit FIFO Underrun Interrupt Enable (TUDRIE). This bit enables an interrupt if the TUDRL bit in the
HSRL
Bit 2: Transmit FIFO Low Watermark Interrupt Enable (TLWMIE). This bit enables an interrupt if the TLWML bit
in the
Bit 3: Receive FIFO High Watermark Interrupt Enable (RHWMIE). This bit enables an interrupt if the RHWML bit
in the
Bit 4: Receive Abort Sequence Detected Interrupt Enable (RABTIE). This bit enables an interrupt if the RABTL
bit in the
Bit 5: Receive Packet Start Interrupt Enable (RPSIE). This bit enables an interrupt if the RPSL bit in the
register is set.
Bit 6: Receive Packet-End Interrupt Enable (RPEIE). This bit enables an interrupt if the RPEL bit in the
register is set.
Bit 7: Receive FIFO Overrun Interrupt Enable (ROVRIE). This bit enables an interrupt if the ROVRL bit in the
HSRL
HSRL
HSRL
register is set.
register is set.
register is set.
0 = interrupt disabled
1 = interrupt enabled
0 = interrupt disabled
1 = interrupt enabled
0 = interrupt disabled
1 = interrupt enabled
0 = interrupt disabled
1 = interrupt enabled
0 = interrupt disabled
1 = interrupt enabled
0 = interrupt disabled
1 = interrupt enabled
0 = interrupt disabled
1 = interrupt enabled
0 = interrupt disabled
1 = interrupt enabled
HSRL
register is set.
register is set.
ROVRIE
register is set.
7
0
RPEIE
6
0
HSRIE
HDLC Status Register Interrupt Enable
56h
RPSIE
5
0
RABTIE
HSRIE
59 of 89
4
0
register and the HDLCIE bit in the
RHWMIE
3
0
TLWMIE
2
0
TUDRIE
1
0
MSRIE
register are
TENDIE
0
0
HSRL
HSRL