CY7C68300A-56PVXC Cypress Semiconductor Corp, CY7C68300A-56PVXC Datasheet
![no-image](/images/manufacturer_photos/0/1/179/cypress_semiconductor_corp_sml.jpg)
CY7C68300A-56PVXC
Specifications of CY7C68300A-56PVXC
Available stocks
Related parts for CY7C68300A-56PVXC
CY7C68300A-56PVXC Summary of contents
Page 1
... USB port and one ATA- or ATAPI-based mass storage device port. This bridge adheres to the Mass Storage Class Bulk-Only Transport Specification and is intended for self-powered devices. The USB port of the CY7C68300A is connected to a host computer directly or via the downstream port of a USB hub. Host software CY7C68300A and receives status and data from the CY7C68300A using standard USB protocol ...
Page 2
... Document #: 38-08031 Rev. *C The device initialization process is configurable, enabling the CY7C68300A to initialize ATA/ATAPI devices without software intervention. DD13 DD14 DD15 GND NC Vcc GND IORDY DMARQ AVcc XTALOUT VBUS_PWR_VALID XTALIN EZ-USB AT2 AGND CY7C68300A Vcc 56-pin SSOP DPLUS DMINUS GND Vcc GND ...
Page 3
... Hi-Z ATA Data bit 13. Hi-Z ATA Data bit 14. Hi-Z ATA Data bit 15. Ground. Hi-Z Reserved. This pin should remain a no-connect Connect to 3.3V power source. CC Ground. I ATA Control. I ATA Control. Analog V possible. CY7C68300A 42 RESET# 41 GND 40 ARESET# 39 VBUS_PWR_VALID 38 CS1# 37 CS0# 36 DA2 35 DA1 34 DA0 ...
Page 4
... Hi-Z ATA Data bit 6. Hi-Z ATA Data bit 7. Ground Connect to 3.3V power source. CC Ground. ATA Control. ATA Control. ATA Control Connect to 3.3V power source. CC IDE ATA Interrupt request. CY7C68300A Pin Description 2 C-compatible interface (see section 2 C-compatible interface (see section 3.2.2). Page ...
Page 5
... CY7C68300A will resume only long enough to stop driving the ATA interface (High-Z) and drop back to low-power again. • If the CY7C68300A is already in suspend and ATA_EN transitions to '1', the CY7C68300A will resume only long enough to start driving the ATA interface and drop to low- power again ...
Page 6
... VBUS_PWR_VALID VBUS_PWR_VALID indicates to the CY7C68300A that power is present on VBUS. This pin is polled by the CY7C68300A at start-up and then every 20ms thereafter. If this pin is ‘1’, the 1.5K pull-up is attached to D+. If this pin is ‘0’, the CY7C68300A will release the pullup required by the USB specification ...
Page 7
... Reserved (must be zero) 6.1.2.1 Mfg_load During a mfg_load, the CY7C68300A goes into Manufacturing Test Mode. Manufacturing Test Mode is provided as a means to implement board or system level interconnect tests. During Manufacturing Test Mode operation, all outputs not directly associated with USB operation are controllable ...
Page 8
... Reserved 6.1.2.2 Mfg_read This USB request returns a “snapshot in time” of select CY7C68300A input pins. The input pin states are bit-wise mapped to the ATAPI data associated with this request. CY7C68300A input pins not directly associated with USB Table 6-5. Mfg_read Data Format ...
Page 9
... At least one reset must be enabled. Do not set SRST to 0 and Skip Pin Reset to 1at the same time. 4. SRST Enable must be set in conjunction with Skip Pin Reset. Setting this bit causes the CY7C68300A to bypass ARESET# during initialization. All reset events except a power-on reset utilize SRST as the drive mechanism. ...
Page 10
... Bit (7) Enable Ultra DMA data transfer support for ATAPI devices. If enabled, and if the ATAPI device reports UDMA support for the indicated modes, the CY7C68300A will utilize UDMA data transfers at the highest negotiated rate possible Disable ATA device UDMA support Enable ATA device UDMA support. ...
Page 11
... The value to use as an argument to Set Configuration to select the configuration. This value must be set to 0x01. Index to the configuration string. This entry must equal half of the address value where the string starts or 0x00 if the string does not exist. CY7C68300A Required Suggested Contents Contents ...
Page 12
... Length of configuration descriptor in bytes. Descriptor type. Number of bytes returned in this configuration. This includes the configuration descriptor plus all the interface and endpoint descriptors. Number of interfaces supported. The value to use as an argument to Set Configuration to select the configuration. CY7C68300A Required Suggested Contents Contents 0xC0 0x00 0x09 ...
Page 13
... Endpoint descriptor type. This is an Out endpoint, endpoint number 2. This is a bulk endpoint. Max data transfer size. Does not apply to FS bulk endpoints. Must be set to 0. LANGID string descriptor length in bytes. Descriptor type. CY7C68300A Required Suggested Contents Contents 0x00 0xC0 0x00 ...
Page 14
... Unicode character. (“NUL”) Unicode character. (“NUL”) Unicode character. (“NUL”) Unicode character. (“NUL”) Unicode character. (“NUL”) Unicode character. CY7C68300A Required Suggested Contents Contents 0x09 0x04 0x2C 0x03 “C” 0x43 0x00 “y” 0x79 0x00 “ ...
Page 15
... Unicode character. (“NUL”) Unicode character. (“NUL”) Unicode character. (“NUL”) Unicode character. (“NUL”) Unicode character. (“NUL”) Unicode character. CY7C68300A Required Suggested Contents Contents 0x00 “o” 0x6F 0x00 “r” 0x72 0x00 0x2C 0x03 “U” 0x55 0x00 “ ...
Page 16
... Unicode character. (“NUL”) Unicode character. (“NUL”) Unicode character. (“NUL”) Unicode character. (“NUL”) Unicode character. (“NUL”) Unicode character. (“NUL”) CY7C68300A Required Suggested Contents Contents 0x00 “i” 0x69 0x00 “c” 0x63 0x00 “e” 0x65 0x00 ...
Page 17
... A Copper (Cu) fill designed into the PCB as a thermal pad under the package. Heat is transferred from the CY7C68300A through the device’s metal paddle on the bottom side of the package. Heat from here is conducted to the PCB at the thermal pad then conducted from the thermal pad to the PCB inner ground plane array of Via ...
Page 18
... Certain design considerations must be followed to ensure proper operation of the CY7C68300A. 9.1 Proper Power-up Sequence Power must be applied to the CY7C68300A before the same time as the ATA/ATAPI device. If power is supplied to the drive first, the CY7C68300A will start undefined state. Designs that utilize separate power supplies for the CY7C68300A and the ATA/ATAPI device are not recom- mended ...
Page 19
... Ordering Information Part Number CY7C68300A-56PVC 56-pin SSOP CY7C68300A-56LFC 56-pin QFN CY7C68300A-56PVXC 56-pin Lead(Pb)-free SSOP CY7C68300A-56LFXC 56-pin Lead(Pb)-Free QFN CY4615A EZ-USB AT2 Reference Design Kit Note alternate clock source is input on XTALIN it must be supplied with standard 3.3V signaling characteristics and XTALOUT must be left floating. ...
Page 20
... SIDE VIEW 0.08[0.003] C 1.00[0.039] MAX. 0.05[0.002] MAX. 0.80[0.031] MAX. 0.20[0.008] REF. 0.30[0.012] 0.50[0.020] 0°-12° C SEATING PLANE 2 C system, provided that the system conforms to the I CY7C68300A DIMENSIONS IN INCHES MIN. MAX. 0.005 0.010 0.024 0.040 51-85062-*C BOTTOM VIEW 0.18[0.007] 0.28[0.011] PIN1 ID N 0.20[0.008 ...
Page 21
... Document History Page Description Title: CY7C68300A EZ-USB AT2™ USB 2.0 to ATA/ATAPI Bridge Document Number: 38-08031 Issue REV. ECN NO. Date ** 124022 02/13/03 *A 124857 06/06/03 *B 129094 08/18/03 *C 285992 SEE ECN Document #: 38-08031 Rev. *C Orig. of Change GIR New data sheet GIR Updated overall language/layout for “Final” status Revised description of DPLUS pin in section 2 ...