MAX15066EWE+T Maxim Integrated Products, MAX15066EWE+T Datasheet - Page 8

• Manufacturer Part Number: MAX15066EWE+T
• Description: DC/DC Switching Controllers 4A 12V 500kHz w/Integrated Switch
• Manufacturer: Maxim Integrated Products

Specifications of MAX15066EWE+T

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

High-Efficiency, 4A, Step-Down DC-DC
Regulator with Internal Power Switches
8
B1, B2, B3
C2, C3
BUMP
A1, A2
A3, A4
______________________________________________________________________________________
C1
C4
D1
D2
D3
D4
B4
PGOOD
NAME
COMP
GND
V
BST
I.C.
EN
FB
SS
LX
IN
DD
Ground. Connect A1 and A2 together as close as possible to the device.
Power-Supply Input. Input supply range is from 4.5V to 16V. Connect A3 and A4 together as close as
possible to the device. Bypass IN to GND with a minimum 22FF ceramic capacitor as close as
possible to the device.
Inductor Connection. Connect an inductor between LX and the regulator output. LX is high
impedance when the device is in shutdown mode. Connect all LX nodes together as close as possible
to the device.
Internal 5V LDO Output. V
capacitor from V
High-Side MOSFET Driver Supply. Bypass BST to LX with a 0.01FF capacitor. BST is internally
connected to the V
Internal Connection. Leave unconnected.
Enable Input. Connect EN to GND to disable the device. Set EN to above 1.9V (typ) to enable the
device. EN can be shorted to IN for always-on operation.
Power-Good Output. PGOOD is an open-drain output that goes high impedance when V
0.56V (typ). PGOOD is internally pulled low when V
pulled low when the device is in shutdown mode, V
thermal shutdown.
Feedback Input. Connect FB to the center tap of an external resistor-divider from the output to GND to
set the output voltage from 0.606V to 90% of V
Voltage-Error Amplifier Output. Connect the necessary compensation network from COMP to GND
(see the Compensation Design section).
Soft-Start Timing Capacitor Connection. Connect a capacitor from SS to GND to set the startup time
(see the Setting the Soft-Start Time section).
(BUMPS ON BOTTOM)
TOP VIEW
DD
DD
to GND.
+
regulator through a pMOS switch.
PGOOD
GND
BST
A1
LX
B1
C1
D1
DD
powers the internal analog core. Connect a minimum of 1FF ceramic
GND
I.C.
A2
LX
B2
C2
FB
D2
WLP
COMP
I.C.
C3
D3
A3
B3
IN
LX
FUNCTION
IN
.
V
A4
B4
C4
D4
EN
SS
IN
FB
DD
DD
falls below 0.545V (typ). PGOOD is internally
is below the UVLO threshold, or the device is in
Pin Configuration
Pin Description
FB
exceeds