DP83955AV National Semiconductor, DP83955AV Datasheet - Page 24
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DP83955AV
Manufacturer Part Number
DP83955AV
Description
IC CTRLR RIC REPEATER 100-PQFP
Manufacturer
National Semiconductor
Series
LERIC™r
Datasheet
1.DP83955AV.pdf
(54 pages)
Specifications of DP83955AV
Controller Type
LitE Repeater Interface Controller
Voltage - Supply
5V
Current - Supply
250mA
Mounting Type
Surface Mount
Package / Case
84-LCC (J-Lead)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Operating Temperature
-
Interface
-
Other names
*DP83955AV
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DP83955AV
Manufacturer:
NS/国半
Quantity:
20 000
SEND PREAMBLE state The LERIC system utilizes the
SEND DATA is followed but is not visible upon the Inter-
LISION state (described later) This behavior is known as
5 0 Functional Description
The repeater is stimulated into activity by the data signal
received by port B1 The LERICs in the system are alerted
to forthcoming repeater operation by the falling edges on
the ACKI –ACKO daisy chain and the ACTN bus signal Fol-
lowing a defined start up delay the repeater moves to the
start up delay to perform port arbitration When packet
transmission begins the LERIC system enters the REPEAT
state The expected for normal packet repetition sequence
of repeater states SEND PREAMBLE SEND SFD and
LERIC bus They are merged together into a single REPEAT
state This is also true for the WAIT and IDLE states they
appear as a combined Inter-LERIC bus IDLE state
Once a repeat operation has begun (i e
leaves the IDLE state) it is required to transmit at least
96 bits of data or jam preamble onto its network segments
If the duration of the received signal from PORT N is smaller
than 96 bits the repeater transitions to the RECEIVE COL-
fragment extension
After the packet data has been repeated including the emp-
tying of the LERICs’ elasticity buffers the LERIC performs
the Tw1 transmit recovery operation This is performed dur-
ing the WAIT state shown in the repeater state diagram
Receive Collisions
A receive collision is a collision which occurs on the network
segment attached to PORT N (i e
ceived’’ in a similar manner as a data packet is received and
then repeated to the other network segments) Not surpris-
ingly receive collision propagation follows a similar se-
quence of operations as is found with data repetition
An arbitration process is performed to find PORT N and a
preamble jam pattern is transmitted by the repeater’s other
ports When PORT N detects a collision on its segment the
COLN Inter-LERIC bus signal is asserted This forces all the
LERICs in the system to transmit a preamble jam pattern to
their segments This is important since they may be already
transmitting data from their elasticity buffers The repeater
the collision is ‘‘re-
(Continued)
the repeater
24
moves to the RECEIVE COLLISION state when the LERICs
begin to transmit the jam pattern The repeater remains in
this state until both the following conditions have been ful-
filled
1 At least 96 bits have been transmitted onto the network
2 The activity has ended
Under close examination the repeater specification reveals
that the actual end of activity has its own permutations of
conditions
1 Collision and receive data signals may end simulta-
2 Receive data may appear to end before collision signals
3 Receive data may continue for some time after the end
Network segments using coaxial media may experience
spurious gaps in segment activity when the collision signal
goes inactive This arises from the inter-action between the
receive and collision signal squelch circuits implemented in
coaxial transceivers and the properties of the coaxial cable
itself The repeater specification avoids propagation of
these activity gaps by extending collision activity by the Tw2
wait time Jam pattern transmission must be sustained
throughout this period After this the repeater will move to
the WAIT state unless there is a data signal being received
by PORT N
The functional timing diagram Figure 5-5 shows the opera-
tion of a repeater system during a receive collision The
system configuration is the same as earlier described and is
shown in Figure 5-3
The LERICs perform the same PORT N arbitration and data
repetition operations as previously described The system is
notified of the receive collision on port B1 by the COLN bus
signal going active This is the signal which informs the main
state machines to output the jam pattern rather than the
data held in the elasticity buffers Once a collision has oc-
curred the IRC IRD and IRE bus signals may become unde-
fined When the collision has ended and the Tw2 operation
performed the repeater moves to the WAIT state
neously
of the collision signal