DP83955AV National Semiconductor, DP83955AV Datasheet - Page 39

• Manufacturer Part Number: DP83955AV
• Description: IC CTRLR RIC REPEATER 100-PQFP
• Manufacturer: National Semiconductor
• Series: LERIC™r

Specifications of DP83955AV

• Controller Type: LitE Repeater Interface Controller
• Voltage - Supply: 5V
• Current - Supply: 250mA
• Mounting Type: Surface Mount
• Package / Case: 84-LCC (J-Lead)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Operating Temperature: -
• Interface: -
• Other names: *DP83955AV

7 0 LERIC Registers
7 1 LERIC REGISTER ADDRESS MAP
The LERIC’s registers may be accessed by applying the
required address to the four register address (D(7 4)) input
pins Pin D(7) makes the selection between the upper and
Address D(7 4)
0000
1000
0001
1001
0010
1010
0011
1011
0100
1100
0101
1101
0110
1110
0111
1111
Address D(7 4)
0000
1000
0001
1001
0010
1010
0011
1011
0100
1100
0101
1101
0110
1110
0111
1111
DISPT
DISPT
DISPT
DISPT
DISPT
DISPT
DISPT
PART
PART
PART
PART
PART
PART
PART
PART
Resv
D(3)
TABLE 7-1 Register Memory Map
Register Array Bit Map
LERIC Status Register Lower Nibble
LERIC Status Register Upper Nibble
Port 1 Status and Configuration Register Lower Nibble
Port 1 Status and Configuration Register Upper Nibble
Port 2 Status and Configuration Register Lower Nibble
Port 2 Status and Configuration Register Upper Nibble
Port 3 Status and Configuration Register Lower Nibble
Port 3 Status and Configuration Register Upper Nibble
Port 4 Status and Configuration Register Lower Nibble
Port 4 Status and Configuration Register Upper Nibble
Port 5 Status and Configuration Register Lower Nibble
Port 5 Status and Configuration Register Upper Nibble
Port 6 Status and Configuration Register Lower Nibble
Port 6 Status and Configuration Register Upper Nibble
Port 7 Status and Configuration Register Lower Nibble
Port 7 Status and Configuration Register Upper Nibble
39
Resv
Resv
Resv
Resv
Resv
Resv
Resv
Resv
REC
REC
REC
REC
REC
REC
REC
D(2)
JAB
lower nibbles of each register The register map consists of
8 registers as shown in the Register Map in Table 7-1 which
is followed by a summary of the register bits shown in Table
7-2 The definitions for these bits are shown in the detailed
register definitions on the following pages
Name
AREC
Resv
Resv
COL
COL
COL
COL
COL
COL
COL
D(1)
POL
POL
POL
POL
POL
POL
GDLNK
GDLNK
GDLNK
GDLNK
GDLNK
GDLNK
GDLNK
ACOL
SQRL
Resv
Resv
D(0)
SQL
SQL
SQL
SQL
SQL