DP8522AV-25 National Semiconductor, DP8522AV-25 Datasheet
DP8522AV-25
Specifications of DP8522AV-25
Related parts for DP8522AV-25
DP8522AV-25 Summary of contents
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... DP8520A 68 DP8521A 68 DP8522A 84 Block Diagram TRI-STATE is a registered trademark of National Semiconductor Corporation PAL is a registered trademark of and is used under license from Monolithic Memories Inc C 1995 National Semiconductor Corporation TL F 9338 Features On chip high precision delay line to guarantee critical Y VRAM access timing parameters ...
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INTRODUCTION 2 0 SIGNAL DESCRIPTIONS 2 1 Address R W and Programming Signals 2 2 VRAM Control Signals 2 3 Refresh Signals 2 4 Port A Access Signals 2 5 Port B Access Signals (DP8522A Common ...
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Introduction The DP8520A 21A 22A are CMOS Video RAM controllers that incorporate many advanced features including the ca- pabilities of address latches refresh counter refresh clock row column and refresh address multiplexor delay line re- fresh access VRAM ...
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Introduction (Continued) wait signal is active low The user can choose either at pro- gramming These signals are used by the on-chip arbitor to insert wait states to guarantee the arbitration between ac- cesses and refreshes or precharge ...
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Connection Diagrams Order Number DP8520AV-20 or DP8520AV-25 Top View FIGURE 2 See NS Package Number V68A 9338 – 2 ...
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... Connection Diagrams (Continued) Order Number DP8521AV-20 or DP8521AV-25 Order Number DP8522AV-20 or DP8522AV-25 Top View FIGURE 3 See NS Package Number V68A Top View FIGURE 4 See NS Package Number V84A 9338 – 9338– 4 ...
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Signal Descriptions Pin Device (If not Input Name applicable to all) Output 2 1 ADDRESS R W AND PROGRAMMING SIGNALS R0 –10 DP8522A I R0 –9 DP8520A 21A I C0 –10 DP8522A I C0 –9 DP8520A 21A I ...
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Signal Descriptions (Continued) Pin Device (If not Input Name applicable to all) Output 2 3 REFRESH SIGNALS RFIP(RFRQ) O RFSH I DISRFSH PORT A ACCESS ADS I (ALE AREQ I WAIT O ...
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Signal Descriptions (Continued) Pin Device (If not Input Name applicable to all) Output 2 6 COMMON DUAL PORT SIGNALS GRANTB DP8522A O only LOCK DP8522A I only 2 7 VRAM TRANSFER CYCLE SIGNALS AVSRLRQ I VSRL I 2 ...
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Port A Access Modes The DP8520A 21A 22A have two general purpose access modes With one of these modes any microprocessor can be interfaced to VRAM A Port A access to VRAM is initiated by two input signals ...
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Port A Access Modes (Continued) FIGURE 5b Access Mode 0 Extending CAS FIGURE 5a Access Mode 9338 – 9338 – 7 ...
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Port A Access Modes (Continued) FIGURE 6b Access Mode 1 Extending CAS FIGURE 6a Access Mode 9338– 9338– 9 ...
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Refresh Options The DP8520A 21A 22A support a wide variety of refresh control mode options including automatic internally con- trolled refresh externally controlled burst refresh refresh request acknowledge and any combination of the above With each of the ...
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Refresh Options (Continued) Explanation of Terms RFRQ ReFresh ReQuest internal to the DP8520A 21A 22A e RFRQ has the ability to hold off a pending access RFSH Externally requested ReFreSH e RFIP ReFresh In Progress e ACIP Port ...
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Refresh Options (Continued) FIGURE 8 External Burst Refresh (2 Periods of RAS Precharge 2 Periods of Refresh RAS Low during Refresh Programmed) FIGURE 9a Externally Controlled Single and Burst Refresh with Refresh Request (RFRQ) Output (2 Periods of ...
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Refresh Options (Continued) 16 ...
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Refresh Options (Continued Staggered RAS Refresh A staggered refresh staggers each RAS or group of RASs by a positive edge of CLK as shown in Figure 11 The num- ber of RASs which will be ...
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Refresh Options (Continued EXTENDING REFRESH The programmed number of periods of CLK that refresh RASs are asserted can be extended by one or multiple peri- ods of CLK Only the all RAS (with or without error ...
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Port A Wait State Support Wait states allow a CPU’s access cycle to be increased by one or multiple CPU clock periods The wait or ready input is named differently by CPU manufacturers However any CPU’s wait or ...
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Port A Wait State Support 5 3 WAIT STATE SUPPORT FOR VIDEO RAM SHIFT REGISTER LOAD OPERATIONS FOR PORT A If using the DP8520A 21A 22A in a system using video VRAMs the CPU that controls loading the ...
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Port A Wait State Support 5 4 DYNAMICALLY INCREASING THE NUMBER OF WAIT STATES The user can increase the number of positive edges of CLK before DTACK is asserted or WAIT is negated With the input WAITIN asserted ...
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Port A Wait State Support FIGURE 20 WAITIN Example (WAIT is Sampled at the End of ‘‘T2’’) FIGURE 21 Guaranteeing RAS Precharge (DTACK is Sampled at the ‘‘T2’’ Falling Clock Edge) (Continued 9338 – 76 ...
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... The DP8520A 21A 22A support of video RAMs allows the full capabilities of the National Semiconductor Advanced Graphics chip set (DP8500 Series realized See Fig- ures 22 23 and 58a ...
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DP8520A 21A 22A Video RAM Support 6 1 SUPPORT FOR VRAM TRANSFER CYCLES (TO THE SERIAL PORT OF THE VRAM) The DP8520A 21A 22A supports VRAM transfer cycles with the serial port in the active or standby mode ...
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DP8520A 21A 22A Video RAM Support FIGURE 24 Video RAM Timing READ Transfer Cycle B Port Active (Transfer VRAM Row Data into Shift Register) FIGURE 25 Video RAM Timing WRITE Transfer Cycle B Port Active (Transfer Shift Register ...
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DP8520A 21A 22A Video RAM Support During a transfer cycle (VSRL asserted during the access) WIN is disabled from affecting the DT OE logic until the transfer cycle is completed as shown by CAS negating Dur- ing a ...
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DP8520A 21A 22A Video RAM Support 6 2 SUPPORT FOR VRAM ACCESS CYCLES THROUGH PORT A USING THE DP8520A 21A 22A With the DP8520A 21A 22A the output DT OE will remain negated during write accesses (see Figure ...
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Additional Access Support Features To support the different modes of accessing the DP8520A 21A 22A have multiple access features These features al- low the user to take advantage of CPU or VRAM functions These additional features include address ...
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Additional Access Support Features FIGURE 30 Non-Address Pipelined Mode (Continued) FIGURE 29 Column Increment FIGURE 31 Address Pipelined Mode 9338 – 9338 – 9338 – 82 ...
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Additional Access Support Features 30 ...
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Additional Access Support Features 7 3 DELAY CAS DURING WRITE ACCESSES Address bit C9 asserted during programming will cause CAS to be delayed until the first positive edge of CLK after RAS is asserted when the input WIN ...
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RAS and CAS Configuration Modes The DP8520A 21A 22A allow the user to configure the VRAM array to contain one two or four banks of VRAM Depending on the functions used certain considerations must be used when determining ...
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RAS and CAS Configuration Modes FIGURE 37 VRAM Array Setup for 16-Bit 1 Bank System ( FIGURE 38 8 Bank VRAM Array ( (Continued Allowing Error Scrubbing ...
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RAS and CAS Configuration Modes 8 2 MEMORY INTERLEAVING Memory interleaving allows the cycle time of VRAMs to be reduced by having sequential accesses to different memory banks Since the DP8520A 21A 22A have separate pre- charge counters ...
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RAS and CAS Configuration Modes FIGURE 40 VRAM Array Setup for 4 Banks Using Address Pipelining ( (Also Allowing Error Scrubbing) during Programming) e FIGURE 41 VRAM Array Setup ...
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RAS and CAS Configuration Modes 8 5 PAGE BURST MODE In a static column page or burst mode system the least significant bits must be tied to the column address in order to ensure that the page burst ...
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Programming and Resetting The DP8520A 21A 22A must be programmed by one of two possible programming sequences before it can be used After power up the DP8520A 21A 22A must be externally reset (see External Reset) before programming ...
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Programming and Resetting Using this method various programming schemes can be used For example if extra upper address bits are available an unused high order address bit can be tied to the signal ML Using this method one ...
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Programming and Resetting 9 3 EXTERNAL RESET At power up if the internal power up reset worked all inter- nal latches and flip-flops are cleared The power up state is entered by asserting ML and DISRFSH for 16 ...
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Programming and Resetting 9 4 PROGRAMMING BIT DEFINITIONS Symbol ECAS0 Extend CAS Refresh Request Select 0 The CASn outputs will be negated with the RASn outputs when AREQ (or AREQB DP8522A only) is negated The RFIP pin will ...
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Programming and Resetting 9 4 PROGRAMMING BIT DEFINITIONS (Continued) Symbol RAS and CAS Configuration Modes (Continued RAS pairs are selected by B1 CAS0– 3 are all selected For a particular CAS to ...
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Programming and Resetting 9 4 PROGRAMMING BIT DEFINITIONS (Continued) Symbol R7 WAIT or DTACK Select 0 WAIT type output is selected 1 DTACK (Data Transfer ACKnowledge) type output is selected R6 Add Wait States to the Current Access ...
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Test Mode Staggered refresh in combination with the error scrubbing mode places the DP8520A 21A 22A in test mode In this mode the 24-bit refresh counter is divided into a 13-bit and 11-bit counter During refreshes both counters ...
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Dual Accessing Functions (DP8522A) The DP8522A has all the functions previously described In addition to those features the DP8522A also has the capa- bilities to arbitrate among refresh Port A and a second port Port B This allows ...
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Dual Accessing Functions (DP8522A PORT B WAIT STATE SUPPORT (DP8522A) Advanced transfer acknowledge for Port B ATACKB is used for wait state support for Port B This output will be asserted when RAS for the Port ...
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Dual Accessing Functions (DP8522A) Since the DP8522A has only one set of address inputs the signal is used with the addition of buffers to allow the cur- rently granted port’s addresses to reach the DP8522A The signals which ...
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Dual Accessing Functions (DP8522A) FIGURE 58b Wait States during a Port B Access LOCK Input When the LOCK input is asserted the currently granted port can ‘‘lock out’’ the other port through the insertion of ...
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... Absolute Maximum Ratings If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Temperature under Bias Storage Temperature Electrical Characteristics Symbol Parameter V Logical 1 Input Voltage Tested with a Limited IH Functional Pattern V Logical 0 Input Voltage ...
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AC Timing Parameters DP8520A DP8521A DP8522A Number Symbol 1 fCLK CLK Frequency 2 tCLKP CLK Period 3 4 tCLKPW CLK Pulse Width 5 fDCLK DELCLK Frequency 6 tDCLKP DELCLK Period 7 8 tDCLKPW DELCLK Pulse Width 9a tPRASCAS0 ...
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AC Timing Parameters DP8520A DP8521A DP8522A Unless otherwise stated 10 per bank including trace capacitance (see Note 2) Two different loads are specified loads on all outputs ...
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AC Timing Parameters DP8520A DP8521A DP8522A Unless otherwise stated 10 per bank including trace capacitance (see Note 2) Two different loads are specified loads on all outputs ...
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AC Timing Parameters DP8520A DP8521A DP8522A Unless otherwise stated 10 per bank including trace capacitance (see Note 2) Two different loads are specified loads on all outputs ...
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AC Timing Parameters DP8520A DP8521A DP8522A Unless otherwise stated 10 per bank including trace capacitance (see Note 2) Two different loads are specified loads on all outputs ...
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AC Timing Parameters DP8520A DP8521A DP8522A Unless otherwise stated 10 per bank including trace capacitance (see Note 2) Two different loads are specified loads on all outputs ...
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AC Timing Parameters DP8520A DP8521A DP8522A Unless otherwise stated 10 per bank including trace capacitance (see Note 2) Two different loads are specified loads on all outputs ...
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AC Timing Parameters DP8520A DP8521A DP8522A Unless otherwise stated 10 per bank including trace capacitance (see Note 2) Two different loads are specified loads on all outputs ...
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AC Timing Parameters DP8520A DP8521A DP8522A Unless otherwise stated 10 per bank including trace capacitance (see Note 2) Two different loads are specified loads on all outputs ...
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AC Timing Parameters DP8520A DP8521A DP8522A FIGURE 60 Clock DELCLK Timing FIGURE 61 100 Dual Access Port B 58 (Continued 9338 – 9338– B6 ...
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AC Timing Parameters DP8520A DP8521A DP8522A FIGURE 62 100 Port A and Port B Dual Access FIGURE 63 200 Refresh Timing 59 (Continued 9338 – 9338 – B8 ...
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AC Timing Parameters DP8520A DP8521A DP8522A FIGURE 64 300 Mode 0 Timing 60 (Continued 9338– B9 ...
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AC Timing Parameters DP8520A DP8521A DP8522A (Programmed FIGURE 65 300 Mode 0 Interleaving 61 (Continued 9338 – C0 ...
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AC Timing Parameters DP8520A DP8521A DP8522A FIGURE 66 400 Mode 1 Timing 62 (Continued 9338 – C1 ...
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AC Timing Parameters DP8520A DP8521A DP8522A FIGURE 67 400 COLINC Page Static Column Access Timing FIGURE 68 500 Programming 63 (Continued 9338 – 9338 – C3 ...
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AC Timing Parameters DP8520A 21A 22A (Continued) FIGURE 69 Graphics Timing Diagram 9338 – 57 ...
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Functional Differences between the DP8520A 21A 22A and the DP8520 Extending the Column Address Strobe (CAS) CAS can be extended indefinitely after AREQ transitions high in non-interleaved mode only providing that the user program the ...
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Description of a DP8522A DP8500 System Interface FIGURE 70 DP8422A DP8500 (RGP) Interface Block Diagram The main idea of the block diagram in Figure cause the video DRAM shift register load operation to happen cor- ...
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Description of a DP8522A DP8500 System Interface FIGURE 71 DP8522A DP8500 (RGP) Instruction Read Cycle Timing 67 (Continued 9338– C5 ...
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Description of a DP8522A DP8500 System Interface FIGURE 72 DP8500 (20 MHz) DP8522A FIGURE 73 Mid-Scan Line Load Application Example Write Operand Cycle Timing 68 (Continued 9338– 9338– C7 ...
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Description of a DP8522A DP8500 System Interface (Continued) 69 ...
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... Physical Dimensions inches (millimeters) Order Number DP8520AV-20 DP8520AV-25 DP8521AV-20 or DP8521AV-25 Order Number DP8522AV-20 or DP8522AV-25 LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION As used herein ...