DP83907VF National Semiconductor, DP83907VF Datasheet - Page 10

• Manufacturer Part Number: DP83907VF
• Description: IC CONTROLLR AT/LANII TP 160PQFP
• Manufacturer: National Semiconductor

Specifications of DP83907VF

• Controller Type: Network Interface Controller (NIC)
• Interface: Twisted Pair
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 150mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 160-MQFP, 160-PQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *DP83907VF

4 0 Functional Description
The DP83907’s internal memory map is accessed one byte
or word at a time via a port within the systems I O space
DP83907 is programmed by the user to control the transfers
between its internal memory and the I O port
DP83907’s internal registers and the memory access port
are accessed within the system’s I O map The address
within this I O map is set by Configuration Register A
16-BIT I O PORT COMPATIBLE MODE I O ADDRESS
MAPPING
This mode is compatible with Novell’s NE2000 Architecture
The base I O address of DP83907 is configured by Configu-
ration Register A (either upon power up or by software writ-
ing to this register) At the base I O address the following
stwcture appears
FIGURE 3 I O Port Mode Register I O Map
Base
Base
Base
Base
Base
Base
a
a
a
a
a
a
17h
00h
0Fh
10h
18h
1Fh
FIGURE 2 I O Port
Data Transfer
Reset Port
Register
DP8390
Core
Port
(Continued)
TL F 12082–5
The
10
The DP83907 register space within this area are 8 bits wide
but the data transfer port is 16 bits wide The DP83907’s
registers can be programmed to control the passing of data
between its internal memory and the data transfer port By
accessing the data transfer port (using I O instructions) the
user can transfer data to or from the DP83907’s internal
memory The DP83907’s internal memory map is as shown
below
DP83907 has a 64k address range but only does partial
decoding through this space The PROM data is mirrored
from all decodes up to 4000H and the entire map is repeat-
ed at 8000H To access either the PROM or the RAM the
user must initiate a Remote DMA transfer between the I O
port and memory
001Eh
001Ch
0008h
0006h
0004h
0002h
0000h
00Ah
FIGURE 4 a) NIC Core’s 16-Bit Memory Map
001Fh
7FFFh
C000h
0000h
4000h
8000h
FFFh
b) 16-Bit PROM Map
D15
00
00
00
00
00
00
00
00
00
D15
(a)
(b)
00
Aliased PROM
Aliased PROM
Buffer RAM
Buffer RAM
8k x 16
Aliased
E’net Address 5
E’net Address 4
E’net Address 3
E’net Address 2
E’net Address 1
E’net Address 0
RESERVED
57h
57h
D0
PROM
D0