DP83907VF National Semiconductor, DP83907VF Datasheet - Page 65

• Manufacturer Part Number: DP83907VF
• Description: IC CONTROLLR AT/LANII TP 160PQFP
• Manufacturer: National Semiconductor

Specifications of DP83907VF

• Controller Type: Network Interface Controller (NIC)
• Interface: Twisted Pair
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 150mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 160-MQFP, 160-PQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *DP83907VF

Symbol
T27
T28a
T28b
T30
T31
T33
T35
T36
T38
Preliminary Switching Design Guidelines
ISA SLAVE ACCESSES (Continued)
Note 1 M16 IO16 are only asserted for 16-bit transfers
Note 2 CHRDY is only deasserted if the NIC core can not service the access immediately It is held deasserted until the NIC core is ready causing the system to
insert wait states
Note 3 On 8-bit transfers only 8 bits of MSD0–15 and D0–7 are driven
Note 5 This is the standard CHRDY timing where CHRDY is asserted after IORD or IOWR
Note 6 Read data valid is referenced to CHRDY when wait states have been inserted
Note 7 If no wait states are inserted read data valid can be measured from IORD
Note 8 This is a minimum timing with no additional wait states
Note 9 This is the standard IO16 timing where IO16 is asserted after a valid address decode
Note 10 This is the late IO16 timing required by some machines where IO16 is asserted after a valid address decode and IORD or IOWR going active
Note 11 This is a timing for a RAM access
Note 13 This is a timing for a Boot PROM access
Note 14 Guaranteed by design
SERIAL EEPROM TIMING
Note 1 Derived from crystal oscillator tolerance
Symbol
T1
T2
T3
T4
T5
T6
T7
T8
SA0–19 Valid to BPCS Asserted (Note 11)
MRD Asserted to MSRD Asserted
MWR Asserted to MSWR Asserted
SA0–19 Invalid to BPCS Negated (Note 11)
SMRD Deasserted to MSRD Deasserted
MSWR Deasserted to MSD0–7 Invalid (Note 3)
BPCS Asserted to CHRDY Asserted (Note 13)
MSRD Asserted to CHRDY Asserted (Note 13)
MSD0-7 Asserted to CHRDY Asserted (Note 13)
EECS Setup to MSD2
EECS Hold after MSD2
MSD2 Low Time
MSD2 High Time
MSD2 Clock Period (Note 1)
MSD1 Setup to MSD2 High
MSD2 Hold from MSD2 High
MSD0 Valid from MSD2 High
Description
Description
e
g
0 01%
65
(Continued)
Min
175
150
250
8-Bit Transfers
0
0
0
Min
150
250
450
450
100
100
1
Max
120
55
60
Max
500
16-Bit Transfers
Min
Max
120
55
60
TL F 12082 – 46
Units
ns
ns
ns
ns
ns
ns
ns
s
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns