DP83934CVUL-25 National Semiconductor, DP83934CVUL-25 Datasheet - Page 50

• Manufacturer Part Number: DP83934CVUL-25
• Description: IC CTRLR ORIENT NETWORK 160PQFP
• Manufacturer: National Semiconductor

Specifications of DP83934CVUL-25

• Controller Type: Network Interface Controller (NIC)
• Interface: Twisted Pair
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 140mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 160-MQFP, 160-PQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *DP83934CVUL-25

15 –12
6 0 SONIC-T Registers
6 3 7 Data Configuration Register 2
(RA
This register (Figure 6-10) is for enabling the extended bus interface options
A hardware reset will set all bits in this register to ‘‘0’’ except for the Extended Programmable Outputs which are unknown until
written to A software reset will not affect any bits in this register This register should only be written to when the SONIC-T is in
software reset (the RST bit in the Command Register is set)
Bit
11
9
8
7
6
5
4
3
k
EXPO3 EXPO2 EXPO1 EXPO0 HD
5 0
r w
15
l
EXPO
These bits program the level of the Extended User outputs (EXUSR
Writing a ‘‘1’’ to any of these bits programs a high level to the corresponding output Writing a ‘‘0’’ to any of these
bits programs a low level to the corresponding output EXUSR
EXUSR
Section 6 3 2)
HD HEART BEAT DISABLE
This bit allows the SONIC-T to ignore the heart beat signal
0 Enable heart beat
1 Disable heart beat
JD TPI JABBER TIMER DISABLE
This bit allows the user to turn on off the jabber timer
0 Enable the jabber timer
1 Disable the jabber timer
AUTO AUI TPI AUTO SELECTION
This bit allows the SONIC-T to check for a good link on the TPI and AUI SONIC-T will first look for a good link on the
TPI If there is no good link on the TPI SONIC-T will automatically select the AUI If this bit is enable the AUI TPI pin
will be ignored
0 Disable AUI TPI auto selection
1 Enable AUI TPI auto selection
Must be zero
XWRAP TPI TRANSCEIVER LOOPBACK
This bit controls the loopback operation for the TPI transceiver For proper operation the CAM Address Registers
and Receiver Control Register must be initialized to accept the destination address of the loopback packet (refer to
loopback procedure) Also both bits 9 and 10 of the RCR must be set to 1
0 Disable TPI transceiver loopback
1 Enable TPI transceiver loopback
Must be zero
PH PROGRAM HOLD
When this bit is set to ‘‘0’’ the HOLD request output is asserted deasserted from the falling edge of bus clock If this
bit is set to ‘‘1’’ HOLD will be asserted deasserted
Must be zero
e
3Fh)
r w
14
k
k
3 0
3 0
l
l
r w
EXTENDED PROGRAMMABLE OUTPUTS
13
are only available when the Extended Bus mode is selected (bit 15 in the DCR is set to ‘‘1’’ see
r w
12
(Continued)
EXPO3–0 EXTENDED PROGRAMMABLE OUTPUTS
HD
JD
AUTO
XWRAP
PH
PCM
PCNM
RJCM
Field
r w r w r w
11
FIGURE 6-10 Data Configuration Register 2
10
0
HEART BEAT DISABLE
TPI JABBER TIMER DISABLE
AUI TPI AUTO SELECTION
TPI TRANSCEIVER LOOPBACK
PROGRAM HOLD
PACKET COMPRESS WHEN MATCHED
PACKET COMPRESS WHEN NOT MATCHED
REJECT ON CAM MATCH
JD
9
AUTO
r w
8
50
Description
clock later on the rising edge of bus clock
r w
Meaning
7
0
k
XWRAP
3 0
r w
6
l
k
3 0
are similiar to USR
r w r w r w
l
5
0
) when the SONIC-T is a bus master
PH
4
3
0
k
PCM PCNM RJCM
r w
1 0
2
l
except that
r w
1
r w
0