DP83936AVUL-25 National Semiconductor, DP83936AVUL-25 Datasheet - Page 58

• Manufacturer Part Number: DP83936AVUL-25
• Description: IC CTRLR ORIENT NETWORK 160PQFP
• Manufacturer: National Semiconductor

Specifications of DP83936AVUL-25

• Controller Type: Network Interface Controller (NIC)
• Interface: Twisted Pair
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 140mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 160-MQFP, 160-PQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *DP83936AVUL-25

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Figures 7-3 and 7-4 show the National Intel (BMODE
(Figure 7-3) When the SONIC-T needs to access the bus it
7 0 Bus Interface
7 3 1 Acquiring The Bus
The SONIC-T requests the bus when 1) its FIFO threshold
has been reached or 2) when the descriptor areas in memo-
ry (i e RRA RDA CDA and TDA) are accessed Note that
when the SONIC-T moves from one area in memory to an-
other (e g RBA to RDA) it always deasserts its bus request
and then requests the bus again when accessing the next
area in memory
The SONIC-T provides two methods to acquire the bus for
compatibility with National Intel or Motorola type microproc-
essors These two methods are selected by setting the
proper level on the BMODE pin
and Motorola (BMODE
tions of each mode follows For both modes when the
SONIC-T relinquishes the bus there is an extra holding
state (Th) for one bus cycle after the last DMA cycle (T2)
This assures that the SONIC-T does not contend with an-
other bus master after it has released the bus
BMODE
The National Intel processors require a 2-way handshake
using a HOLD REQUEST HOLD ACKNOWLEDGE protocol
issues a HOLD REQUEST (HOLD) to the microprocessor
The microprocessor responds with a HOLD ACKNOWL-
EDGE (HLDA) to the SONIC-T The SONIC-T then begins
its memory transfers on the bus As long as the CPU main-
tains HLDA active the SONIC-T continues until it has fin-
ished its memory block transfer The CPU however can
preempt the SONIC-T from finishing the block transfer by
deasserting HLDA before the SONIC-T deasserts HOLD
This allows a higher priority device to preempt the SONIC-T
from continuing to use the bus The SONIC-T will request
the bus again later to complete any operation that it was
doing at the time of preemption The HLDA signal is sam-
pled synchronously by the SONIC-T at the rising edge of the
BSCK setup time must be met to ensure proper operation
www national com
e
0
e
1) bus request timing Descrip-
(Continued)
FIGURE 7-3 Bus Request Timing (BMODE
e
0)
58
As shown in Figure 7-3 the SONIC-T will assert HOLD to
either the falling or rising edge of the bus clock (BSCK) The
default is for HOLD to be asserted on the falling edge Set-
ting the PH bit in the DCR2 (see Section 6 4 7) causes
HOLD to be asserted
(shown by the dotted line) Before HOLD is asserted the
SONIC-T checks the HLDA line If HLDA is asserted HOLD
will not be asserted until after HLDA has been deasserted
first
Note If HLDA is driven low to preempt the SONIC-T from the bus while the
BMODE
The Motorola protocol requires a 3-way handshake using a
BUS REQUEST BUS GRANT and BUS GRANT AC-
KNOWLEDGE handshake (Figure 7-4) When using this pro-
tocol the SONIC-T requests the bus by lowering BUS RE-
QUEST BR The CPU responds by issuing BUS GRANT BG
Upon receiving BG the SONIC-T assures that all devices
have relinquished control of the bus before using the bus
The following signals must be deasserted before the SON-
IC-T acquires the bus
Deasserting BGACK indicates that the previous master has
released the bus Deasserting AS indicates that the previ-
ous master has completed its cycle and deasserting
DSACK0 1 and STERM indicates that the previous slave
has terminated its connection to the previous master The
SONIC-T maintains its mastership of the bus until it deas-
serts BGACK It can not be preempted from the bus
BGACK
AS
DSACK0 1
STERM (Asynchronous Mode Only)
SONIC-T is accessing the CAM (LCAM command) the SONIC-T will
get off the bus but will not deassert HOLD even though the status bit
will indicate idle state If HLDA is driven low while the SONIC-T is
accessing descriptor areas (RRA RDA TDA) the SONIC-T will be
preempted normally (i e get off the bus and deassert HOLD) and the
HOLD signal will be reasserted again after one bus clock If HLDA is
driven low while the SONIC-T is accessing data areas (RBA TBA)
the SONIC-T will be preempted normally but may not reassert HOLD
unless required to do so depending on the threshold condition of the
FIFO
e
1
e
0)
bus clock later on the rising edge
TL F 12597 – 30