MAX5935CAX Maxim Integrated Products, MAX5935CAX Datasheet
MAX5935CAX
Specifications of MAX5935CAX
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MAX5935CAX Summary of contents
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... Current Foldback and Duty-Cycle- Controlled/Programmable Current Limit ♦ Short-Circuit Protection with Fast Gate Pulldown ♦ Direct Fast Shutdown Control Capability ♦ Programmable Direct Interrupt Output ♦ Watchdog Mode Enable Hardware Graceful Takeover PART MAX5935CAX MAX5935CAX+ MAX5935EAX MAX5935EAX+ Applications Features , Common-Mode DIG to (AGND + 7.7V) EE ...
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... Maximum Power Dissipation 36-Pin SSOP (derate 11.4mW/°C above +70°C) .........941mW Operating Temperature Ranges: MAX5935EAX ..................................................-40°C to +85°C MAX5935CAX .....................................................0°C to +70°C Storage Temperature Range .............................-65°C to +150°C Junction Temperature ......................................................+150°C Lead Temperature (soldering, 10s) .................................+300°C = (DGND + 3.3V +25° ...
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ELECTRICAL CHARACTERISTICS (continued) (AGND = +48V 0V DGND = +3.3V. All voltages are referenced values are at AGND = +48V, DGND = +48V, V negative otherwise.) PARAMETER SYMBOL Minimum Foldback Current- V ...
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Quad Network Power Controller for Power-Over-LAN ELECTRICAL CHARACTERISTICS (continued) (AGND = +48V 0V DGND = +3.3V. All voltages are referenced values are at AGND = +48V, DGND = +48V, V negative otherwise.) ...
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ELECTRICAL CHARACTERISTICS (continued) (AGND = +48V 0V DGND = +3.3V. All voltages are referenced values are at AGND = +48V, DGND = +48V, V negative otherwise.) PARAMETER SYMBOL Internal Input Pullup/Pulldown R ...
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Quad Network Power Controller for Power-Over-LAN ELECTRICAL CHARACTERISTICS (continued) (AGND = +48V 0V DGND = +3.3V. All voltages are referenced values are at AGND = +48V, DGND = +48V, V negative otherwise.) ...
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AUTO = AGND = DGND = 0, RESET = SHD_ = unconnected -48V all registers = default setting, unless otherwise noted.) DIGITAL SUPPLY CURRENT vs. INPUT VOLTAGE 6 MEASURED ...
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Quad Network Power Controller for Power-Over-LAN = +3.3V, AUTO = AGND = DGND = 0, RESET = SHD_ = unconnected -48V all registers = default setting, unless otherwise noted.) OVERCURRENT TIMEOUT (R = 240Ω ...
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AUTO = AGND = DGND = 0, RESET = SHD_ = unconnected -48V all registers = default setting, unless otherwise noted.) OVERCURRENT RESTART DELAY 400ms/div DETECTION WITH INVALID PD (25kΩ AND 10µF) ...
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Quad Network Power Controller for Power-Over-LAN = +3.3V, AUTO = AGND = DGND = 0, RESET = SHD_ = unconnected -48V all registers = default setting, unless otherwise noted.) DETECTION WITH MIDSPAN MODE WITH ...
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PIN NAME Hardware Reset. Pull RESET low for at least 300µs to reset the device. All internal registers reset to RESET 1 their default value. The address (A0–A3), and AUTO and MIDSPAN input logic levels latch on during low-to-high transition ...
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Quad Network Power Controller for Power-Over-LAN V SCL SDAIN SDAOUT SHD_ DD SERIAL PORT INTERFACE (SPI REGISTER FILE A3 AUTO MIDSPAN CENTRAL LOGIC UNIT (CLU) RESET INT AGND ANALOG +10V ANALOG BIAS/ SUPPLY +5V DIG MONITOR VOLTAGE ...
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PD that draws more current than the allowable amount for its class. The MAX5935’s extensive programmability enhances sys- tem flexibility and allows for uses in other applications. The MAX5935 ...
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Quad Network Power Controller for Power-Over-LAN Setting R19h[PWR_ON_] (Table 21) high immediately terminates detection/classification routines and turns on power to the port(s). R14h[DET_EN_, CLASS_EN_] default to low in SEMI mode. Use software to set R14h[DET_EN_, CLASS_EN_] to high to start ...
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Table 1. PSE PI Detection Modes Electrical Requirement (Table 33-2 of the IEEE 802.3af Standard) PARAMETER SYMBOL Open-Circuit Voltage V OC Short-Circuit Current I SC Valid Test Voltage V VALID Voltage Difference Between ∆V TEST Test Points Time Between Any ...
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Quad Network Power Controller for Power-Over-LAN 150ms 150ms 80ms DETI DETII 0V -4V -9V OUT_ -18V -48V Figure 2. Detection, Classification, and Power-Up Port Sequence t PGOOD POK PGOOD Figure 3. PGOOD Timing 16 ______________________________________________________________________________________ A sense ...
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V ) SENSE_ EE V SU_LIM SU_LIM 30V Figure 4. Foldback Current Characteristics MOSFET Gate Driver Connect the gate of the external n-channel MOSFET to GATE_. An internal 50µA current source pulls GATE_ to (V ...
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Quad Network Power Controller for Power-Over-LAN The MAX5935 also features three other undervoltage and overvoltage interrupts: V undervoltage interrupt undervoltage interrupt (V EEUV DD overvoltage interrupt ( fault latches into the DDOV supply events ...
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SDAIN t SU, DAT t LOW SCL t HIGH t HD, STA t R START CONDITION Figure 5. 2-Wire Serial Interface Timing Details SDAIN/SDA t LOW SCL t HIGH t HD, STA t R START CONDITION Figure 6. 3-Wire Serial ...
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Quad Network Power Controller for Power-Over-LAN START CONDITION SCL SDA BY TRANSMITTER S SDA BY RECEIVER Figure 9. Acknowledge MSB 0 SDA 1 SCL Figure 10. Slave Address Each clock pulse transfers one data bit (Figure 8). The data on ...
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CONTROL BYTE IS STORED ON RECEIPT OF STOP CONDITION S SLAVE ADDRESS Figure 11. Control Byte Received HOW CONTROL BYTE AND DATA BYTE MAP INTO THE REGISTER ACKNOWLEDGE FROM MAX5935 S SLAVE ADDRESS R/W Figure 12. Control and Single Data ...
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Quad Network Power Controller for Power-Over-LAN Table 4. Auto-Increment Rules COMMAND BYTE AUTO-INCREMENT BEHAVIOR ADDRESS RANGE Command address will auto- 0x00 to 0x26 increment after byte read or written Command address remains at 0x26 0x26 after byte written or read ...
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Table 5. Interrupt Register ADDRESS = 00h SYMBOL BIT R/W Interrupt signal for supply faults. SUP_FLT is the logic OR of all the bits [7:0] in register R0Ah/R0Bh SUP_FLT 7 R (Table 8). Interrupt signal for startup failures. TSRT_FLT is ...
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Quad Network Power Controller for Power-Over-LAN Table 7. Power Event Register ADDRESS = 02h 03h SYMBOL BIT R/W R/W PG_CHG4 7 R CoR PG_CHG3 6 R CoR PG_CHG2 5 R CoR PG_CHG1 4 R CoR PWEN_CHG4 3 R CoR PWEN_CHG3 ...
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Table 10. Startup Event Register ADDRESS = 08h SYMBOL BIT R/W IVC4 7 R IVC3 6 R IVC2 5 R IVC1 4 R STRT_FLT4 3 R STRT_FLT3 2 R STRT_FLT2 1 R STRT_FLT1 0 R Table 11. Supply Event Register ...
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Quad Network Power Controller for Power-Over-LAN Table 12a. Detection Result Decoding Chart DET_ST_[2:0] DETECTED 000 None Detection status unknown. 001 DCP Positive DC supply connected at the port (AGND - V 010 HIGH CAP High capacitance at the port (>5µF). ...
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Table 13. Power Status Register ADDRESS = 10h SYMBOL BIT R/W PGOOD4 7 R Power-good condition on Port 4 PGOOD3 6 R Power-good condition on Port 3 PGOOD2 5 R Power-good condition on Port 2 PGOOD1 4 R Power-good condition ...
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Quad Network Power Controller for Power-Over-LAN Setting BCKOFF_ to 1 (Table 18) enables cadence timing on each port, where the port backs off and waits 2.2s after each failed load discovery detection. The IEEE 802.3af standard requires a PSE that ...
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Table 18. Backoff Enable Register ADDRESS = 15h SYMBOL BIT R/W Reserved 7 R Reserved Reserved 6 R Reserved Reserved 5 R Reserved Reserved 4 R Reserved BCKOFF4 3 R/W Enable Cadence timing on Port 4 BCKOFF3 2 R/W Enable ...
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Quad Network Power Controller for Power-Over-LAN Table 20. Miscellaneous Configurations ADDRESS = 17h SYMBOL BIT R/W A logic high enables INT functionality INT_EN 7 R/W RSTR_EN logic high enables the auto-restart protection time off (as set by ...
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Table 23. ID Register ADDRESS = 1Bh SYMBOL BIT R ID_CODE[ ID_CODE[3] ID_CODE 5 R ID_CODE[ ID_CODE[ ID_CODE[ REV [2] REV 1 R REV [ REV [0] ID ...
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Quad Network Power Controller for Power-Over-LAN Table 25. Watchdog Timer Register ADDRESS = 1Eh SYMBOL BIT R/W 7 R/W WDTIME[7] 6 R/W WDTIME[6] 5 R/W WDTIME[5] 4 R/W WDTIME[4] WDTIME 3 R/W WDTIME[3] 2 R/W WDTIME[2] 1 R/W WDTIME[1] 0 ...
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Table 27. Program Register 1 ADDRESS = 23h SYMBOL BIT R/W 7 R/W IGATE[2] IGATE 6 R/W IGATE[1] 5 R/W IGATE[0] DET_BYP 4 R/W Detect bypass protection in AUTO mode OSCF_RS 3 R/W OSC_FAIL Reset Bit 2 R/W AC_TH[2] AC_TH ...
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Quad Network Power Controller for Power-Over-LAN Table 29. Program Register 3 ADDRESS = 28h SYMBOL BIT R TF_PR[3 TF_PR[2]. t TF_PR 5 R TF_PR[1 TF_PR[0 TS_PR[3 ...
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Quad Network Power Controller ______________________________________________________________________________________ for Power-Over-LAN 35 ...
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Quad Network Power Controller for Power-Over-LAN 36 ______________________________________________________________________________________ ...
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PSE (SWITCHES/ROUTER, ETC.) DATA PHY POWER MAX5020 3.3V -48V TO +3.3V DC-DC GND -48V Figure 14. PoE System Block Diagram ______________________________________________________________________________________ Quad Network Power Controller PD (IP PHONE, WIRELESS ACCESS POINT, SECURITY CAMERAS, ETC.) RJ–45 RJ–45 POWER AND DATA OVER ...
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Quad Network Power Controller for Power-Over-LAN PHY ISOLATION V (3.3V) CC 1.8V TO 5V, (REF TO DGND) 180Ω 3kΩ HPCL063L VCCRTN OPTIONAL BUFFER 180Ω HPCL063L SDA OPTIONAL BUFFER 180Ω HPCL063L SCL OPTIONAL BUFFER Figure 15. PoE System Diagram of One ...
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ISOLATION V (3.3V (REF TO DGND) 180Ω 3kΩ HPCL063L VCCRTN OPTIONAL BUFFER 180Ω SDA OPTIONAL BUFFER 180Ω SCL OPTIONAL BUFFER Figure 16. PoE System Diagram of One Complete Port, Midspan PSE ______________________________________________________________________________________ Quad Network Power Controller ...
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Quad Network Power Controller for Power-Over-LAN R10 2Ω R6 1Ω C3 15nF Q4 MMBTA56 GND GND 1 MAX5020 0.47µF 4 100V SS_SHDN C2 0.022µF -48V -48V Figure 17. -48V to +3.3V (300mA) Boost ...
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Component List DESIGNATION DESCRIPTION C1 0.1µF, 25V ceramic capacitor C2 0.022µF, 25V ceramic capacitor C3 15nF, 25V ceramic capacitor 220µF capacitor C4 Sanyo 6SVPA220MAA C5 4.7µF, 16V ceramic capacitor C6 0.1µF, 100V ceramic capacitor C7 0.22µF, 16V ceramic capacitor C8 ...
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Quad Network Power Controller for Power-Over-LAN ISOLATION V (3.3V) CC 3kΩ VCCRTN HPCL063L OPTIONAL BUFFER 180Ω SDA OPTIONAL BUFFER 180Ω SCL OPTIONAL BUFFER NOTE: ALL SIGNAL PINS ARE REFERENCED TO DGND. DGND RANGE IS BETWEEN V Typical Operating Circuit 1 ...
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ISOLATION V (3.3V) CC (REF TO DGND) 3kΩ 180Ω HPCL063L VCCRTN OPTIONAL BUFFER 180Ω SDA OPTIONAL BUFFER 180Ω SCL OPTIONAL BUFFER NOTE: ALL SIGNAL PINS ARE REFERENCED TO DGND. DGND MUST BE CONNECTED DIRECTLY TO AGND FOR AC DISCONNECT DETECTION ...
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... Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 44 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2007 Maxim Integrated Products DIM ...