MAX5935CAX Maxim Integrated Products, MAX5935CAX Datasheet - Page 11

• Manufacturer Part Number: MAX5935CAX
• Description: Hot Swap & Power Distribution
• Manufacturer: Maxim Integrated Products

Specifications of MAX5935CAX

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

22, 25,
23, 26,
24, 27,
11–14
17–20
29, 32
30, 33
31, 34
7–10
PIN
15
16
21
28
35
36
1
2
3
4
5
6
SENSE4, SENSE3,
SENSE2, SENSE1
GATE4, GATE3,
GATE2, GATE1
A3, A2, A1, A0
SHD1, SHD2,
OUT4, OUT3,
SHD3, SHD4
OUT2, OUT1
DET1, DET2,
DET3, DET4
MIDSPAN
SDAOUT
OSC_IN
RESET
SDAIN
NAME
DGND
AGND
AUTO
SCL
V
V
INT
DD
EE
______________________________________________________________________________________
Hardware Reset. Pull RESET low for at least 300µs to reset the device. All internal registers reset to
their default value. The address (A0–A3), and AUTO and MIDSPAN input logic levels latch on during
low-to-high transition of RESET. Internally pulled up to V
MIDSPAN Mode Input. An internal 50kΩ pulldown resistor to DGND sets the default mode to endpoint
PSE operation (power-over-signal pairs). Pull MIDSPAN TO VDIG to set MIDSPAN operation. The
MIDSPAN value latches after the IC is powered up or reset (see the PD Detection section).
Open-Drain Interrupt Output. INT goes low whenever a fault condition exists. Reset the fault condition
using software or by pulling RESET low (see the Interrupt section of the Detailed Description for more
information about interrupt management).
Serial Interface Clock Line
Serial Output Data Line. Connect the data line optocoupler input to SDAOUT (see the Typical
Application Circuit). Connect SDAOUT to SDAIN if using a 2-wire I
Serial Interface Input Data Line. Connect the data line optocoupler output SDAIN (see the Typical
Application Circuit). Connect SDAIN to SDAOUT if using a 2-wire wire I
Address Bit. A3, A2, A1, and A0 form the lower part of the device’s address. Address inputs default
high with an internal 50kΩ pullup resistor to V
up and exceeds its UVLO threshold or after a reset. The 3 MSB bits of the address are set to 010.
Detection and Classification Voltage Output. Use DET1 to set the detection and classification probe
voltages on port 1. Use DET1 for the AC voltage sensing of port 1 when using the AC disconnect
scheme (see the Typical Application Circuit).
Connect to Digital Ground
Positive Digital Supply. Connect to digital supply (referenced to DGND).
Port Shutdown Input. Pull SHD_ low to turn-off the external FET on port_. Internally pulled up to V
with a 50kΩ resistor.
Analog Ground. Connect to the high-side analog supply.
MOSFET Source Current-Sense Negative Input. Connect to the source of the power MOSFET and
connect a current-sense resistor between SENSE_ and V
Port_ MOSFET Gate Driver. Connect GATE_ to the gate of the external FET (see the Typical
Application Circuit).
MOSFET Drain-Output Voltage Sense. Connect OUT_ to the power MOSFET drain through a resistor
(100Ω to 100kΩ). The low leakage at OUT_ limits the drop across the resistor to less than 100mV
(see the Typical Application Circuit).
Low-Side Analog Supply Input. Connect the low-side analog supply to V
capacitor between AGND and V
AUTO or SHUTDOWN Mode Input. Force high to enter AUTO mode after a reset or power-up. Drive
low to put the MAX5935 into SHUTDOWN mode. In SHUTDOWN mode, software controls the
operational modes of the MAX5935. A 50kΩ internal pulldown resistor defaults AUTO low. AUTO
latches when V
Software commands can take the MAX5935 out of AUTO while AUTO is high.
Oscillator Input. AC-disconnect detection function uses OSC_IN. Connect a 100Hz ±10%, 2V
±5%, +1.2V offset sine wave to OSC_IN. If the oscillator positive peak falls below OSC_FAIL
threshold of 2V, the ports that have the AC function enabled shut down and are not allowed to power
up. When not using the AC-disconnect detection function, leave OSC_IN unconnected.
Quad Network Power Controller
DD
or V
EE
ramps up and exceeds its UVLO threshold or when the device resets.
EE
.
FUNCTION
DD
for Power-Over-LAN
. The address values latch when V
DD
EE
with a 50kΩ resistor.
(see the Typical Application Circuit).
2
C-compatible system.
2
C-compatible system.
EE
Pin Description
(-48V). Bypass with a 1µF
DD
or V
EE
ramps
P-P
DD
11