AD9835BRUZ Analog Devices Inc, AD9835BRUZ Datasheet - Page 3

• Manufacturer Part Number: AD9835BRUZ
• Description: IC DDS 10BIT 50MHZ 16-TSSOP
• Manufacturer: Analog Devices Inc

Specifications of AD9835BRUZ

• Resolution (bits): 10 b
• Master Fclk: 50MHz
• Tuning Word Width (bits): 32 b
• Voltage - Supply: 4.75 V ~ 5.25 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP
• Transmitting Current: 5mA
• Rf Ic Case Style: TSSOP
• No. Of Pins: 16
• Supply Voltage Range: 4.75V To 5.25V
• Operating Temperature Range: -40°C To +85°C
• Msl: MSL 3 - 168 Hours
• Termination Type: SMD
• Rohs Compliant: Yes
• Filter Terminals: SMD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-AD9835EBZ - BOARD EVALUATION FOR AD9835
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Parameter
t
t
t
t
t
t
t
t
t
t
t
t
NOTES
1
Guaranteed by design but not production tested.
TIMING CHARACTERISTICS
REV. 0
See Pin Description section.
1
2
3
4
5
6
7
8
9
10
11
11A
1
FSYNC
SDATA
Limit at
T
(B Version)
20
8
8
50
20
20
15
20
SCLK – 5
15
5
8
8
SCLK
MIN
to T
MAX
PSEL0, PSEL1
t
7
D15
FSELECT
(V
MCLK
DD
Units
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns min
ns min
ns min
ns min
= +5 V
D14
t
6
VALID DATA
t
5
Figure 4. Control Timing
Figure 3. Serial Timing
Figure 2. Master Clock
5%; AGND = DGND = 0 V, unless otherwise noted)
MCLK
t
4
t
D2
11
Test Conditions/Comments
MCLK Period
MCLK High Duration
MCLK Low Duration
SCLK Period
SCLK High Duration
SCLK Low Duration
FSYNC to SCLK Falling Edge Setup Time
FSYNC to SCLK Hold Time
Data Setup Time
Data Hold Time
FSELECT, PSEL0, PSEL1 Setup Time Before MCLK Rising Edge
FSELECT, PSEL0, PSEL1 Setup Time After MCLK Rising Edge
–3–
t
2
VALID DATA
t
1
t
3
t
9
D1
t
10
D0
t
t
8
11A
VALID DATA
D15
D14
AD9835