AD5930YRUZ Analog Devices Inc, AD5930YRUZ Datasheet - Page 6

• Manufacturer Part Number: AD5930YRUZ
• Description: IC GEN PROG FREQ BURST 20TSSOP
• Manufacturer: Analog Devices Inc

Specifications of AD5930YRUZ

• Resolution (bits): 10 b
• Master Fclk: 50MHz
• Tuning Word Width (bits): 24 b
• Voltage - Supply: 2.3 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 20-TSSOP
• Synthesizer Type: Frequency
• Frequency: 25MHz
• Supply Voltage Range: 2.3V To 5.5V
• Supply Current: 2.4mA
• Operating Temperature Range: -40°C To +105°C
• Digital Ic Case Style: TSSOP
• No. Of Pins: 20
• Pin Count: 20
• Screening Level: Automotive
• Package Type: TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

AD5930
TIMING CHARACTERISTICS
All input signals are specified with tr = tf = 5 ns (10% to 90% of V
See Figure 4 to Figure 7. DV
Table 2.
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
Guaranteed by design, not production tested.
1
Limit at T
20
8
8
25
10
10
5
10
5
3
2 x t
0
10 x t
8 x t
2 x t
2 x t
2 x t
20
FSYNC
SDATA
SCLK
1
1
1
1
1
1
MIN
DD
, T
MAX
= 2.3 V to 5.5 V, AGND = DGND = 0 V, all specifications T
t
7
D15
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns typ
ns typ
ns typ
ns typ
ns typ
ns max
D14
t
6
t
5
Conditions/Comments
MCLK period
MCLK high duration
MCLK low duration
SCLK period
SCLK high time
SCLK low time
FSYNC to SCLK falling edge setup time
FSYNC to SCLK hold time
Data setup time
Data hold time
Minimum CTRL pulse width
CTRL rising edge to IOUT/IOUTB delay (initial pulse, includes initialization)
CTRL rising edge to IOUT/IOUTB delay (initial pulse, includes initialization)
Frequency change to SYNC output, saw sweep, each frequency increment
Frequency change to SYNC output, saw sweep, end of sweep
Frequency change to SYNC output, triangle sweep, end of sweep
MCLK falling edge after 16
CTRL rising edge to MCLK falling edge setup time
MCLK
Figure 4. Serial Timing
Figure 3. Master Clock
Rev. 0 | Page 6 of 28
D2
DD
t
2
t
) and timed from a voltage level of (V
t
4
1
t
t
3
9
D1
t
10
th
D0
clock edge to MSB out
t
8
MIN
to T
MAX
, unless otherwise noted.
IL
D15
+ V
IH
)/2.
D14