AD9951YSVZ Analog Devices Inc, AD9951YSVZ Datasheet - Page 19
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AD9951YSVZ
Manufacturer Part Number
AD9951YSVZ
Description
IC DDS DAC 14BIT 1.8V 48-TQFP
Manufacturer
Analog Devices Inc
Specifications of AD9951YSVZ
Resolution (bits)
14 b
Master Fclk
400MHz
Tuning Word Width (bits)
32 b
Voltage - Supply
1.71 V ~ 1.96 V
Operating Temperature
-40°C ~ 105°C
Mounting Type
Surface Mount
Package / Case
48-TQFP Exposed Pad, 48-eTQFP, 48-HTQFP, 48-VQFP
Data Rate
25Mbps
Rf Ic Case Style
TQFP
No. Of Pins
48
Supply Voltage Range
1.8V To 3.3V
Operating Temperature Range
-40°C To +105°C
Msl
MSL 3 - 168 Hours
Ic Function
Direct Digital Synthesizer
Digital Ic Case Style
TQFP
Svhc
No SVHC (15-Dec-2010)
Rohs Compliant
Yes
Termination Type
SMD
Ic Generic Number
9951
Base Number
9951
Filter Terminals
SMD
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AD9951/PCB - BOARD EVAL FOR AD9951
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AD9951YSVZ
Manufacturer:
AD
Quantity:
1 300
Company:
Part Number:
AD9951YSVZ
Manufacturer:
ADI
Quantity:
102
Company:
Part Number:
AD9951YSVZ
Manufacturer:
ADI
Quantity:
650
Company:
Part Number:
AD9951YSVZ
Manufacturer:
Analog Devices Inc
Quantity:
10 000
External Shaped On-Off Keying Mode Operation
The external shaped on-off keying mode is enabled by writing
CFR1<25> to a Logic 1 and writing CFR1<24> to a Logic 0.
When configured for external shaped on-off keying, the
content of the ASFR becomes the scale factor for the data path.
The scale factors are synchronized to SYNC_CLK via the
I/O UPDATE functionality.
Synchronization; Register Updates (I/O UPDATE)
Functionality of the SYNC_CLK and I/O UPDATE
Data into the AD9951 is synchronous to the SYNC_CLK signal
(supplied externally to the user on the SYNC_CLK pin). The
I/O UPDATE pin is sampled on the rising edge of the
SYNC_CLK.
Internally, SYSCLK is fed to a divide-by-4 frequency divider to
produce the SYNC_CLK signal. The SYNC_CLK signal is pro-
vided to the user on the SYNC_CLK pin. This enables synchro-
nization of external hardware with the device’s internal clocks.
This is accomplished by forcing any external hardware to obtain
its timing from SYNC_CLK. The I/O UPDATE signal coupled
with SYNC_CLK is used to transfer internal buffer contents
TO CORE LOGIC
SYSCLK
Q
D
OSK
Rev. 0 | Page 19 of 28
Q
D
PROFILE<1:0>
into the control registers of the device. The combination of the
SYNC_CLK and I/O UPDATE pins provides the user with
constant latency relative to SYSCLK, and also ensures phase
continuity of the analog output signal when a new tuning word
or phase offset value is asserted. Figure 19 demonstrates an I/O
UPDATE timing cycle and synchronization.
Notes to synchronization logic:
1)
2)
The I/O UPDATE signal is edge detected to generate a
single rising edge clock signal that drives the register bank
flops. The I/O UPDATE signal has no constraints on duty
cycle. The minimum low time on I/O UPDATE is one
SYNC_CLK clock cycle.
The I/O UPDATE pin is set up and held around the rising
edge of SYNC_CLK and has zero hold time and 4 ns setup
time.
SYNC_CLK
0
DISABLE
I/O UPDATE
SCLK
SDI
CS
AD9951