AD9951YSVZ Analog Devices Inc, AD9951YSVZ Datasheet - Page 4
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AD9951YSVZ
Manufacturer Part Number
AD9951YSVZ
Description
IC DDS DAC 14BIT 1.8V 48-TQFP
Manufacturer
Analog Devices Inc
Specifications of AD9951YSVZ
Resolution (bits)
14 b
Master Fclk
400MHz
Tuning Word Width (bits)
32 b
Voltage - Supply
1.71 V ~ 1.96 V
Operating Temperature
-40°C ~ 105°C
Mounting Type
Surface Mount
Package / Case
48-TQFP Exposed Pad, 48-eTQFP, 48-HTQFP, 48-VQFP
Data Rate
25Mbps
Rf Ic Case Style
TQFP
No. Of Pins
48
Supply Voltage Range
1.8V To 3.3V
Operating Temperature Range
-40°C To +105°C
Msl
MSL 3 - 168 Hours
Ic Function
Direct Digital Synthesizer
Digital Ic Case Style
TQFP
Svhc
No SVHC (15-Dec-2010)
Rohs Compliant
Yes
Termination Type
SMD
Ic Generic Number
9951
Base Number
9951
Filter Terminals
SMD
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AD9951/PCB - BOARD EVAL FOR AD9951
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AD9951YSVZ
Manufacturer:
AD
Quantity:
1 300
Company:
Part Number:
AD9951YSVZ
Manufacturer:
ADI
Quantity:
102
Company:
Part Number:
AD9951YSVZ
Manufacturer:
ADI
Quantity:
650
Company:
Part Number:
AD9951YSVZ
Manufacturer:
Analog Devices Inc
Quantity:
10 000
AD9951
AD9951—ELECTRICAL SPECIFICATIONS
Table 1. Unless otherwise noted, AVDD, DVDD = 1.8 V ± 5%, DVDD_I/O = 3.3 V ± 5%, R
Frequency = 20 MHz with REFCLK Multiplier Enabled at 20×. DAC Output Must Be Referenced to AVDD, Not AGND.
Parameter
REF CLOCK INPUT CHARACTERISTICS
DAC OUTPUT CHARACTERISTICS
Frequency Range
Input Capacitance
Input Impedance
Duty Cycle
Duty Cycle with REFCLK Multiplier Enabled
REFCLK Input Power
Resolution
Full-Scale Output Current
Gain Error
Output Offset
Differential Nonlinearity
Integral Nonlinearity
Output Capacitance
Residual Phase Noise @ 1 kHz Offset, 40 MHz A
Voltage Compliance Range
Wideband SFDR
Narrow-Band SFDR
REFCLK Multiplier Disabled
REFCLK Multiplier Enabled at 4×
REFCLK Multiplier Enabled at 20×
REFCLK Multiplier Enabled @ 20×
REFCLK Multiplier Enabled @ 4×
REFCLK Multiplier Disabled
1 MHz to 10 MHz Analog Out
10 MHz to 40 MHz Analog Out
40 MHz to 80 MHz Analog Out
80 MHz to 120 MHz Analog Out
120 MHz to 160 MHz Analog Out
40 MHz Analog Out (±1 MHz)
40 MHz Analog Out (±250 kHz)
40 MHz Analog Out (±50 kHz)
40 MHz Analog Out (±10 kHz)
80 MHz Analog Out (±1 MHz)
80 MHz Analog Out (±250 kHz)
80 MHz Analog Out (±50 kHz)
80 MHz Analog Out (±10 kHz)
120 MHz Analog Out (±1 MHz)
120 MHz Analog Out (±250 kHz)
120 MHz Analog Out (±50 kHz)
120 MHz Analog Out (±10 kHz)
160 MHz Analog Out (±1 MHz)
160 MHz Analog Out (±250 kHz)
160 MHz Analog Out (±50 kHz)
160 MHz Analog Out (±10 kHz)
1
OUT
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Temp
FULL
FULL
25°C
25°C
25°C
FULL
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
FULL
25°C
Min
1
20
4
35
–15
5
–10
AVDD – 0.5
Typ
3
1.5
50
0
14
10
1
2
5
–105
–115
–132
73
67
62
58
52
87
89
91
93
85
87
89
91
83
85
87
89
81
83
85
87
SET
= 3.92 kΩ, External Reference Clock
+3
15
+10
0.6
AVDD + 0.5
Max
400
100
20
65
Unit
MHz
MHz
MHz
pF
kΩ
%
%
dBm
Bits
mA
%FS
µA
LSB
LSB
pF
dBc/Hz
dBc/Hz
dBc/Hz
V
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc