AD9858BSVZ Analog Devices Inc, AD9858BSVZ Datasheet
AD9858BSVZ
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AD9858BSVZ Summary of contents
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FEATURES 1 GSPS internal clock speed GHz input clock (selectable divide-by-2) Integrated 10-bit DAC Excellent phase noise and SFDR 32-bit programmable frequency register Simplified 8-bit parallel and SPI serial control interface Automatic frequency sweeping capability 4 frequency ...
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AD9858 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Electrical Specifications ................................................................... 3 Absolute Maximum Ratings ............................................................ 6 Thermal Performance .................................................................. 6 Explanation of Test Levels ...
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ELECTRICAL SPECIFICATIONS Unless otherwise noted 3.3 V ± 5%, CPV DD Table 1. Parameter 1 REF CLOCK INPUT CHARACTERISTICS Reference Clock Frequency Range (Divider Off ) Reference Clock Frequency Range (Divider On) Duty Cycle at 1 GHz Input ...
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AD9858 Parameter OUTPUT PHASE NOISE CHARACTERISTICS (AT 100 MHz I With 700 MHz REFCLK) OUT At 100 Hz Offset At 1 kHz Offset At 10 kHz Offset At 100 kHz Offset At 1 MHz Offset At 10 MHz Offset PHASE ...
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Parameter TIMING CHARACTERISTICS Serial Control Bus Maximum Frequency Minimum Clock Pulse Width Low (t Minimum Clock Pulse Width High (t Maximum Clock Rise/Fall Time Minimum Data Setup Time ( Minimum Data Hold Time ( Maximum Data ...
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AD9858 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Rating Maximum Junction Temperature 150° CPV Digital Input Voltage Range −0 Digital Output Current 5 mA Storage Temperature Range ...
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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 100 DGND 5 DGND 6 DVDD 7 DVDD ADDR5 13 ADDR4 14 ADDR3 15 ADDR2/IORESET 16 ...
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AD9858 Pin No. Mnemonic I/O 17 SDO O 18 SDIO I/O 19 WR/SCLK I 22 RD/CS I 29, 30 39, AGND I 41, 42, 49, 50, 52, 69, 74, 80, 85, 87, 88 31, 32, 35, 36, AVDD ...
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TYPICAL PERFORMANCE CHARACTERISTICS MARKER 1 [T1] RBW REF LVL –0.59dBm VBW 5dBm 26.0MHz SWT 1 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 START: 0Hz 50MHz/ Figure 3. Wideband SFDR, 26 MHz f MARKER 1 [T1] RBW ...
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AD9858 MARKER 1 [T1] RBW REF LVL –1.60dBm VBW 0dBm 375.0MHz SWT 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 START: 0Hz 50MHz/ Figure 9. Wideband SFDR, 375 MHz f RBW REF LVL VBW 5dBm SWT 0 ...
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FREQUENCY (Hz) Figure 15. Residual Phase Noise, 103 MHz f OUT 0 –10 –20 –30 –40 –50 ...
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AD9858 DELTA 1 [T1] RBW REF LVL 0.0dB VBW 0dBm 0.00000000Hz SWT 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 CENTER 1.55GHz 15MHz/ Figure 21. Fractional Divider Loop SFDR 1550 MHz 150 ...
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REFCLK (MHz) Figure 27. Power Dissipation vs. REFCLK (Single-Tone Mode, f 600 500 400 300 200 100 0 900 1125 0 = REFCLK/5) Figure 28. ...
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AD9858 THEORY OF OPERATION The AD9858 DDS is a flexible device that can address a wide range of applications. The device consists of a numerically controlled oscillator (NCO) with a 32-bit phase accumulator, 14-bit phase offset adjustment, a power efficient ...
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Charge Pump (CP) The charge pump output reference current is determined by an external resistor (~2.4 kΩ), which establishes a 500 μA maximum internal baseline current (I ). The baseline current is scaled to CP0 provide the appropriate drive current ...
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AD9858 When frequency detection occurs, the loop is closed and the loop is locked based on the current programmed for the wide closed-loop mode important that the loop be designed for closed-loop stability while in the wide closed-loop ...
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Single-Tone Mode When in single-tone mode, the AD9858 generates a signal, or tone single desired frequency. This frequency is set by the value loaded by the user into the chip’s FTW register. This frequency can be between 0 ...
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AD9858 A DFRRW value of 0 written to the register stops all frequency sweeping. There is no automated stop-at-a-given-frequency function. The user must calculate the time interval required to reach the final frequency and then issue a command to write ...
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SYSCLK FUD REGISTERED SYNCLK * FUD I/O BUFFER VALUE 1 (ASYNCHRONOUSLY LOADED VIA I/O PORT) MEMORY CONTROL VALUE 0 REGISTER DATA * FUD IS AN INPUT PROVIDED BY THE USER THAT MUST BE SET UP AND HELD AROUND RISING EDGES ...
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AD9858 I/O Port Functionality The I/O port can operate in either serial or parallel programming mode. Mode selection is accomplished via the SPSELECT pin. The ability to read back the contents of a register is provided in both modes to ...
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ADDR[5: D[7: RDHOZ t AHD VALUE SPECIFICATION t 15ns ADV t 5ns AHD t 15ns RDLOV t 10ns RDHOZ Serial Programming Mode In serial programming mode, the I/O port uses a chip select pin ...
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AD9858 REGISTER MAP The registers are listed in Table 6. The serial address and parallel address numbers associated with each of the registers are shown in hexadecimal format. Square brackets [] are used to reference specific bits or ranges of ...
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Register Address (MSB) Name Ser Par Bit 7 Phase 0x08 0x1A Offset 0x1B Not used Word 2 (POW2) Frequency 0x09 0x1C Tuning 0x1D Word 3 0x1E (FTW3) 0x1F Phase 0x0A 0x20 Offset 0x21 Not used Word 3 (POW3) Reserved 0x0B ...
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AD9858 CFR[22]: Auto Clear Phase Accumulator Bit When CFR[22 (default), a new frequency tuning word is applied to the input of the phase accumulator and added to the currently stored value. When CFR[22 this bit automatically ...
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CFR[4:2]: Power-Down Bits Active high (Logic 1) powers down the respective function. Writing a Logic 1 to all three bits causes the device to enter full sleep mode. CFR[4] is used to shut down the analog mixer stage (default = ...
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AD9858 Profile Selection A profile consists of a specific group of memory registers (see Table 6). In the AD9858, each profile contains a 32-bit frequency tuning word and a 14-bit phase offset word. Each profile is selectable via two external ...
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APPLICATIONS INFORMATION FREQUENCY TUNING WORD 32 10 DDS DAC 1GSPS DDS/DAC CLOCK 1000MHz DIVIDER 1/2 2GHz Figure 37. DDS Synthesizer Translation Loop Oscillator (Implemented in Translation Loop Evaluation Board) FREQUENCY TUNING WORD 32 10 DDS DAC 1GSPS DDS/DAC CLOCK 150MHz ...
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AD9858 EVALUATION BOARDS The AD9858 has three different evaluation board designs. The first design is the traditional DDS evaluation board (see Figure 38). In this design, the DDS is clocked and the output is taken directly from the DAC. The ...
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... The TQFP_EP (thermal slug) must be attached to the ground plane or some other large metal mass for thermal transfer. Failure may cause excessive die temperature rise and damage to the device. ORDERING GUIDE Model Temperature Range AD9858BSV –40°C to +85°C 1 AD9858BSVZ –40°C to +85°C AD9858/PCBZ 1 AD9858/FDPCB 1 AD9858/TLPCBZ RoHS Compliant Part ...
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AD9858 NOTES Rev Page ...
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NOTES Rev Page AD9858 ...
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AD9858 NOTES ©2003–2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D03166-0-2/09(C) Rev Page ...