74LVX4245MTCX Fairchild Semiconductor, 74LVX4245MTCX Datasheet - Page 5

• Manufacturer Part Number: 74LVX4245MTCX
• Description: TXRX 8-BIT DUAL 3STATE 24TSSOP
• Manufacturer: Fairchild Semiconductor
• Series: 74LVXr
• Type: Transceiverr

Specifications of 74LVX4245MTCX

• Number Of Drivers/receivers: 8/8
• Voltage - Supply: 2.7 V ~ 5.5 V
• Mounting Type: Surface Mount
• Package / Case: 24-TSSOP
• Logic Family: LVX
• Operating Supply Voltage (typ): 3.3/5V
• Propagation Delay Time: 11.5ns
• Number Of Elements: 1
• Number Of Channels: 8
• Input Logic Level: CMOS
• Output Logic Level: CMOS
• Output Type: 3-State
• Package Type: TSSOP
• Polarity: Non-Inverting
• Logical Function: Bus Transceiver with Voltage Translation
• Operating Supply Voltage (min): 2.7/4.5V
• Operating Supply Voltage (max): 5.5V
• Technology: CMOS
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Additional Features: W/Volt Translation
• Pin Count: 24
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Protocol: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 74LVX4245MTCXTR

C
C
C
Capacitance
Note 10: C
8-Bit Dual Supply Translating Transceiver
The LVX4245 is a dual supply device capable of bidirec-
tional signal translation. This level shifting ability provides
an efficient interface between low voltage CPU local bus
with memory and a standard bus defined by 5V I/O levels.
The device control inputs can be controlled by either the
low voltage CPU and core logic or a bus arbitrator with 5V
I/O levels.
Manufactured on a sub-micron CMOS process, the
LVX4245 is ideal for mixed voltage applications such as
notebook computers using 3.3V CPU’s and 5V peripheral
devices.
Power Up Considerations
To insure the system does not experience unnecessary I
current draw, bus contention, or oscillations during power
up, the following guidelines should be adhered to (refer to
Table 1):
• Power up the control side of the device first. This is the
• OE should ramp with or ahead of V
• The Transmit/Receive control pin (T/R) should ramp with
Please reference Application Note AN-5001 for more detailed information on using Fairchild’s LVX Low Voltage Dual
Supply CMOS Translating Transceivers.
IN
I/O
PD
Device Type
74LVX4245
V
guard against bus contention.
or ahead of V
Symbol
CCA
.
PD
is measured at 10 MHz
Input Capacitance
Input/Output
Capacitance
Power Dissipation
Capacitance (Note 10)
(power up 1st)
CCA
V
, this will ensure that the A Port data
CCA
5V
TABLE 1. Low Voltage Translator Power Up Sequencing Table
Parameter
(power up 2nd)
V
3V
CCB
CCA
. This will help
B A
A B
with V
ramp
T/R
CCA
CC
Typ
4.5
15
55
40
5
• A side data inputs should be driven to a valid logic level.
The above steps will ensure that no bus contention or oscil-
lations, and therefore no excessive current draw occurs
during the power up cycling of these devices. These steps
will help prevent possible damage to the translator devices
and potential damage to other system components.
with V
pins are configured as inputs. With V
power first, the A I/O Port should be configured as inputs
to help guard against bus contention and oscillations.
This will prevent excessive current draw.
ramp
OE
CCA
Units
pF
pF
pF
pF
0V or V
A Side
logic
I/O
CCA
outputs
B Side
I/O
V
V
V
V
V
Conditions
CCA
CCB
CCA
CCB
CC
www.fairchildsemi.com
Open
5.0V
3.3V
5.0V
3.3V
CCA
Floatable Pin
receiving
Allowed
No